I can't believe a busy UCLA professor spending time and energy making these high quality lectures for random youtube watchers! Prof. Razavi, thank you so much. You're a great professor and an amazing human being!
01:25 - Intro and Review 05:36 - Construction of Cascode Amplifier 17:58 - Quiz: Input Resistance of Source Terminal 22:25 - Increasing Voltage Gain of Circuit with Non-Ideal Drain Load 36:00 - Cascode Amplifier with Current Source Load: MOS 42:42 - Cascode Amplifier with Current Source Load: Bipolar 44:20 - Question
Thank you so much professor Razavi. I am learning microelectronics in Korea, but I lost interest in it easily dumping into a lot of expressions and all the math. Nobody helps me and I don't even decide to study myself. You give me clear and easy way to understand the essential of microelectronics and now it becomes the most interesting subject I've learned.
I am a bioengineer who start studie micro/nano technologies and end up liking very much microelectronics, which will be the topic for my master dissertation, and your classes have helping me a lot in this new adventure. Thank you very much! One day we will meet !
At around 10:20 Prof Razavi states that the current into M2 is gm2*v_in. I believe this assumes that there is no channel length modulation. The formula for I_out is much easier if you neglect channel length modulation, but for those that cannot help themselves like me, I got: G_m = (gm2*ro2 + gm1*gm2*ro1*ro2)/(ro2 + ro1*(1+gm1)). If you then multiply by R_out, assume ro2 ≈ ro1, and gm1*ro1 >> 1, you get the same approximation as Prof Razavi: -gm1*ro1*gm2*ro2.
Only one change, i think the G_m should be (gm2*ro2 + gm1*gm2*ro1*ro2)/(ro2 + ro1*(1+gm1*ro2)). Also i think for G_m calculations assuming CLM to be absent is a good enough approximation, as for every topology the result obtained with this approx is similar to the one obtained without it. Be it the basic amplifier stages, or Degeneration stage, or differential stage.
Generate the bias voltage using the Current mirror circuit. Provide the voltage at gate terminal such that all of your transistors are in the saturation region.
at around 17.20 u said that current is generating and is supplied to ro2 and upper M1. My question is how does it happen. It is a current source and Iout should be devided into gm2vin and (Vds/ro2) and not supplied back.
I found the answer Basically we are trying to find the Rout in case of step(a) We are finding Rout in step(a) to find the path of current flow in step(b) To find Rout in step we are applying thevenin in step(a) from below
I can't believe a busy UCLA professor spending time and energy making these high quality lectures for random youtube watchers! Prof. Razavi, thank you so much. You're a great professor and an amazing human being!
Professor has exceptional talent in teaching. I'm grateful for the lectures.
Has made me fall with electrical engineering again; thank you
Dr.Razavi, you are the best teacher I've ever seen!
01:25 - Intro and Review
05:36 - Construction of Cascode Amplifier
17:58 - Quiz: Input Resistance of Source Terminal
22:25 - Increasing Voltage Gain of Circuit with Non-Ideal Drain Load
36:00 - Cascode Amplifier with Current Source Load: MOS
42:42 - Cascode Amplifier with Current Source Load: Bipolar
44:20 - Question
I am amazed by how everything comes together lecture after lecture. Thank you so much professor Razav
Thank you so much professor Razavi. I am learning microelectronics in Korea, but I lost interest in it easily dumping into a lot of expressions and all the math. Nobody helps me and I don't even decide to study myself. You give me clear and easy way to understand the essential of microelectronics and now it becomes the most interesting subject I've learned.
구원받은 중생이 또 여기에 있군
I am a bioengineer who start studie micro/nano technologies and end up liking very much microelectronics, which will be the topic for my master dissertation, and your classes have helping me a lot in this new adventure. Thank you very much! One day we will meet !
Prof Kong is the teacher that I wish that I had 40 years ago.
This is Prof. Behzad Razavi
waiting for this series...thank you very much, sir
At around 10:20 Prof Razavi states that the current into M2 is gm2*v_in. I believe this assumes that there is no channel length modulation. The formula for I_out is much easier if you neglect channel length modulation, but for those that cannot help themselves like me, I got: G_m = (gm2*ro2 + gm1*gm2*ro1*ro2)/(ro2 + ro1*(1+gm1)). If you then multiply by R_out, assume ro2 ≈ ro1, and gm1*ro1 >> 1, you get the same approximation as Prof Razavi: -gm1*ro1*gm2*ro2.
Only one change, i think the G_m should be (gm2*ro2 + gm1*gm2*ro1*ro2)/(ro2 + ro1*(1+gm1*ro2)).
Also i think for G_m calculations assuming CLM to be absent is a good enough approximation, as for every topology the result obtained with this approx is similar to the one obtained without it. Be it the basic amplifier stages, or Degeneration stage, or differential stage.
Yes you are correct , you can refer the same in his book cascode section , the equation is given taking ro1 and ro2 into account
Brilliant Professor
Just incredible!
Gem of a lecture!
Excellent Sir
So far so good
Thanks Mr. Razavi
Thank you professor!
Thanks again for Sir 👍
Simple
15:55 we would have the same Av if the mosfets were in cascade topology, is this random?
36:37 how to bias the circuit. what should be the voltage values applied at the gate for all the transistors
Generate the bias voltage using the Current mirror circuit. Provide the voltage at gate terminal such that all of your transistors are in the saturation region.
@22:53 he says bias current ...is'nt that supposed to be drain current ?
very good teaching
at around 17.20 u said that current is generating and is supplied to ro2 and upper M1. My question is how does it happen. It is a current source and Iout should be devided into gm2vin and (Vds/ro2) and not supplied back.
im wondering the same
i have the same doubt. Is there any reasonable explanation for it?
Same doubt, can someone help me understand why the current has to flow from M2 to M1?
I found the answer
Basically we are trying to find the Rout in case of step(a)
We are finding Rout in step(a) to find the path of current flow in step(b)
To find Rout in step we are applying thevenin in step(a) from below
THE book is complicated to read on your own.Watch these lectures first.
Can we say that the current gain can be given by Gm*Rin? Finally, it will result in Iout/Iin.
If VGs for NMOS is neg the Rout =ro
In 1st example of lec3 while cal Rout M1 is reverse biased so, we can't apply the henric formulae
how did formula at 13:18 come?
Rout of the degenerated Common source
just awesome...…..
what a legend
He is a clear example why one cannot be a good writer or good teacher (maybe a good engineer).
figures that a video where someone actually explains it is filled with high pitch static noise
There is a section as change pen color
Why do we apply input (Vin) to the transistor M2? As it just acts as a amplifier with degeneration??
Thanks
37:51
are you from one of the zombies from the plant vs zombies game 😶🌫? why you need my brain ?
15 13 (1+gmro)r0 +ro
Thanks
26:50