Razavi Electronics 1, Lec 38, Common-Source Stage with Degeneration

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  • Опубліковано 7 січ 2025

КОМЕНТАРІ • 52

  • @NSURESHSRINIVASAPRASANTH
    @NSURESHSRINIVASAPRASANTH 4 роки тому +5

    Excellent explanation with mind blowing applications which are required for a good circuit designer..

  • @chinthalaadireddy2165
    @chinthalaadireddy2165 Рік тому +1

    Awesomeeeeee Prof Razavi..Whole lots of love!

  • @sumukhathreya6653
    @sumukhathreya6653 10 місяців тому +3

    @13:00 shouldn't we consider the drop across the resistor Rs as the condition is Vds >= Vgs-Vth?

    • @janardhananv7002
      @janardhananv7002 6 місяців тому

      yeah... I too noticed that

    • @林佑-z9h
      @林佑-z9h 5 місяців тому +6

      Yes you have to, but the expression and the circuit topology take care of that.
      The expression Vds > Vgs - Vth can be written as: (Vd - Vs)>(Vg - Vs) - Vth, where Vd, Vg, and Vs mean the voltage of drain, gate and source to the ground respectively.
      As you can see the voltage Vs cancel out on both side, leaving only Vd > Vg - Vth. Plugging in the expression of Vd (Vdd-Id*Rd) and Vg (which is Vo) gives you the inequality on the whiteboard.
      Since Vd (instead of Vds) is directly measured from drain to ground, it automatically includes the voltage drop across resistor Rs.

  • @Skrullx273
    @Skrullx273 Рік тому +3

    prof razavi is just exceptional. I wish I could have gotten into ucla just to study under him :(

  • @kanishkgiri
    @kanishkgiri 2 роки тому +6

    Very nicely explained the concept!❤️

    • @jenil151
      @jenil151 2 роки тому

      Kitna padhega brooo😄

    • @kanishkgiri
      @kanishkgiri 2 роки тому +1

      Pdhna pdega bhai!😂😂
      Wrna lag jaenge

  • @boya1827
    @boya1827 5 років тому +4

    Sir I like your youtube name 恐龙, thanks a lot for this videos, I'm struggling to prepare for my electronics exams right now.

  • @shanthoshkumarm6873
    @shanthoshkumarm6873 5 років тому +5

    in 12:28 sir you took the vds for saturation as vdd-IdRd but it should be vdd-IdRd-IdRs right?

    • @umangmittal5965
      @umangmittal5965 5 років тому +3

      Its correct.. because it is wrt ground not source.. Hope this make sense

    • @azusay167
      @azusay167 5 років тому +3

      Vds=Vo-IdRs and Vgs=Vdd-IdRd-IdRs, so IdRs at both side cancels each other.

    • @nutboy2676
      @nutboy2676 4 роки тому +1

      @@azusay167 Ya but I think you mixed Vgs and Vds

    • @k.k.skesava7561
      @k.k.skesava7561 8 місяців тому

      actually we need to consider only vds>vgs-Vth
      but instead of vgs we are considering Vo (voltage between the gate and ground)
      so, similarly in place of Vds i.e. Vdd- (Id*Rd)- (Id*Rs) we are considering Vdd-(Id*Rd) i.e (Voltage between the drain and ground)
      so, Vdd-(Id*Rd) > Vo-Vth
      is the condition instead of
      Vdd- (Id*Rd)- (Id*Rs) > Vgs-Vth
      (PS: even I too got the same doubt initially by after seeing yours and someone elses doubt I thought and came to this conclusion)

  • @saisatish1743
    @saisatish1743 9 років тому +2

    wow....superb sir .............thanks a lot

  • @sandytheartist.
    @sandytheartist. Рік тому +1

    Gain is lower but it's independent of process variations

  • @nampallysairukmangadrohit7347
    @nampallysairukmangadrohit7347 2 роки тому +1

    Sir, V0= Vg + (drop on Rs), why did you consider Vg=V0 @13:33

    • @govindtuli2913
      @govindtuli2913 Рік тому

      yes i was wondering the same

    • @HLicfr
      @HLicfr Рік тому

      I suppose that what you said is Vgs, but when explaining pinch-off at p277 it says that the edge only required Vg-Vth. And V0=Vg

    • @Skrullx273
      @Skrullx273 Рік тому

      V0 = VGS + drop across RS, since VS = drop across RS, V0 = VG

  • @Sourav_Soumyajit
    @Sourav_Soumyajit 2 роки тому

    Gem of a lecture!

  • @umeshud5405
    @umeshud5405 6 років тому +1

    Love you sir 😍😍😍

  • @dimplesaini8062
    @dimplesaini8062 7 років тому +3

    dear sir, at 12:34 when we are checking whether device really in saturation or not, why gate voltage is taken only Vo , it should be Vo-IdRd becz Vgs is equal to that

    • @mohank523
      @mohank523 7 років тому +1

      Here Vo is over all Vgs . over all Vgs= vgs -I'd rs

    • @alexandrosanastasiou1964
      @alexandrosanastasiou1964 6 років тому

      You are almost right, it should be Vo - Id Rs as a total of Vgs

    • @liIilIil-q7j
      @liIilIil-q7j 3 роки тому

      That is what i am talking about..!

  • @chang-seopyuk3785
    @chang-seopyuk3785 4 роки тому +2

    Thanks a lot!

  • @bharathkumarj.k9547
    @bharathkumarj.k9547 3 роки тому

    Thank You Very Much.

  • @jyotisrivastava4078
    @jyotisrivastava4078 5 років тому +2

    The last circuit you are teaching shouldn't its resistance be 1/gm rather than r02?

    • @shikharsrivastava8346
      @shikharsrivastava8346 5 років тому

      actually should be 1/gm2 || r02, i think?

    • @vijayakumarr3519
      @vijayakumarr3519 4 роки тому

      That will be for Diode connected device but that circuit have constant current circuit model. You can see a battery connected between gate and source. What you are saying is for when gate and drain is shorted.

    • @victrixmortalis7823
      @victrixmortalis7823 4 роки тому +1

      what u r talking about is for a Diode Connected load But this is a current source device for which current is coming out of an arbitrary node and going to ground which can be made by an NMOS device in which the gate and source terminals are biased

  • @ryanpanda2527
    @ryanpanda2527 6 років тому +5

    Hi, Long, where can we find the problem solving strategies for electronics I and II ?

    • @dtm7743
      @dtm7743 4 роки тому +2

      You have sedra smith and Razavi's book

  • @mrpossible5696
    @mrpossible5696 6 років тому +2

    Ty

  • @MsRajuprasadbhu
    @MsRajuprasadbhu 4 роки тому

    sir tu se great ho (indian teacher should teach like him)

  • @prasantnair1590
    @prasantnair1590 5 років тому

    At 57:32 Rout = (1+ gmRs)ro + Rs. When ro= infinite, we are still left with Rout = Rs.............isn't it so Sir? Then why are you telling Rout will be infinite in your next video?

    • @rachnaumesh6130
      @rachnaumesh6130 5 років тому +2

      when ro is infinite, Rout = infinite + Rs which is obviously an infinite value

  • @SL-io6em
    @SL-io6em 3 роки тому

    Razavi YYDS!

  • @mnada72
    @mnada72 4 роки тому

    1:02:10 Please upload circuit theory I&II

  • @videosdopedro
    @videosdopedro 6 років тому +1

    why gm vanishes at 18:00 ??

  • @DuyNguyen-kh5tk
    @DuyNguyen-kh5tk 2 роки тому

    checked!

  • @apoorvajain3765
    @apoorvajain3765 Рік тому

    nice

  • @alterguy4327
    @alterguy4327 6 років тому +1

    21:00

  • @ADITYAAGARWAL-o7y
    @ADITYAAGARWAL-o7y 4 місяці тому

    shutup u are crying not me🤧🤧🤧
    never been this happy