PD Lec 39 - CMOS Latch Up | VLSI | Physical Design

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This is a 39th video on VLSI Physical Design Series. In this video we have explained about CMOS latch up problem. This is a phenomenon which occurs inside of std cell and must be understood thoroughly.
Please ask your doubts in comments.
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[@Narennmallya]

This is a very important topic and also a concern. Thanks for sharing 😀👍

[@jammuashish1201]

for output of cmos inverter we take drain of both pmos and nmos right? but you considered output as source to drain

[@vnnmichael]

Sir you are right ! i just commented the same . Glad that someone else noticed the same

[@PiyushMohapatra23MVD010]

Yes, I was thinking the same thing.

[@shubhamsharma192]

Finally i understood the concept of CMOS Lathup

[@jatingupta9377]

nice explanation btw which background music you are using?, its so smoothing

[@balamanikandan6558]

excellent explanation

[@lucashood1343]

Nice explanation ❤

[@raghavendrakumar8488]

you have taken wrong connection in this video you have to take both Pmos and Nmos drains are connected that are out both nmos source is conncetd to vdd and pmos source is connected to vss gate is input

[@MyINDIANway-yx1om]

yes i also get confused due to that

[@vnnmichael]

Output connection is wrong sir . The Drain of both pmos and nmos are connected together to output . You shorted the Source of pmos with Drain of nmos !

[@PiyushMohapatra23MVD010]

Yes, I was thinking the same thing.

[@piyushmohapatra4642]

For output of the CMOS inverter, Drain of PMOS and NMOS should be connected and output should be taken from that

[@VLSIAcademyhub]

Yes

[@M7hero]

You have wrong connection in the nMOS device, the connected terminal should be the drain and not the source of the device.

[@9awan]

This is a more complicated lecture compared to the previous set up til now

[@VLSIAcademyhub]

Is there any issue or topic that you didn't get ?

[@tangaturuvenkateshwerlu]

Very nice

[@agastinrajece1605]

Please check pmos source terminal connected to vdd & Nmos source terminal connected to vss
We get output from connection of both pmos nmos drain terminal

[@agastinrajece1605]

Please check your setup slack formula

[@Engineer884]

yes, he made wrong

[@prithvi_krishna]

input isnt connected to parasitic transistors, so why input > Vdd will affect ?

[@NareshKumar-we6sc]

Excellent 👍

[@mekalagowthami162]

Sir can you please explain guard rings concept .....🙏

[@VLSIAcademyhub]

God ring is a ring of VSS rail around the boundary of every block which is created to prevent any unintended routes going outside the block
Regards
VLSI Academy

[@bhaskarpalagani3810]

Hi sir,
Please cover indetailed information of SVT, HVT, LVT cells?

[@bhaskarpalagani3810]

@@VLSIAcademyhub I'm sharing it to many fresher folks... Thanks sir

[@Shravana_kaushala_Sathyambudhi]

Man its so complex