I guess scan chain reordering and scandef as an input to placement need to emphasized clearly. Also the initial comment of only a limited scan flops in a design could leave anyone with an idea that many flops are not scannable. That's not the case is current designs. Almost all flops are scannable
It is still not the case, when you have more area in the design then only you could afford to have lot of scan able flops In latest tech nodes, it is still possible to have many flops not scannable
Sir one doubt. If end cap cells are used to prevent manufacturing defects then why even go with scan chain inputs for checking if manufacturing defect was present or not..
@@VLSIAcademyhub Thanks for u r response, I'm following all u r videos and sharing to my friends also. Pls give a detailed explanation of Synthesis flow, so it will be very useful for us.
Ideally d banking shouldn't affect the scan chain connectivity however there is a chance that scan chain length might not be fully optimised. At the beginning of placement we have option to debank flops
scannable flops are flops present in one particular high fanout path.... these differ from normal flops as they have that additional mux that chooses test/func mode. This is given by DFT people..am I correct until here? .so my doubt basically is only flops present in scan chain have that extra mux logic? and there is only one such scannable path per design?
Thank you for your detailed explanation about scan chain ordering 👍 now it clear all my doubts
Your videos are really productive and helps in making concept clear. Thank you so much for your efforts. 🙏
simple and excellent explanation
want more info on CTS stage
keep doing sir.
if possible please avoid the background music
I guess scan chain reordering and scandef as an input to placement need to emphasized clearly. Also the initial comment of only a limited scan flops in a design could leave anyone with an idea that many flops are not scannable. That's not the case is current designs. Almost all flops are scannable
It is still not the case, when you have more area in the design then only you could afford to have lot of scan able flops
In latest tech nodes, it is still possible to have many flops not scannable
Very nice...
Sir plzz increase the frequency of the videos..plz sirr
Sir one doubt.
If end cap cells are used to prevent manufacturing defects then why even go with scan chain inputs for checking if manufacturing defect was present or not..
Sir can you explain about the scan violations and fixing methods
Hi sir your videos are very useful for learning the concepts easily, can u pls upload synthesis flow.
@@VLSIAcademyhub
Thanks for u r response,
I'm following all u r videos and sharing to my friends also.
Pls give a detailed explanation of Synthesis flow, so it will be very useful for us.
Is it valid, if I see sin pin at input at FF in functional mode?
what happens to scan chain if we do banking or debanking of flops in place stage? Kindy throw some light on this aspect.
Ideally d banking shouldn't affect the scan chain connectivity however there is a chance that scan chain length might not be fully optimised. At the beginning of placement we have option to debank flops
test signal not go in the combinational path how will you check combinational path defect ?
We check it w.r.t. through scan chain
scannable flops are flops present in one particular high fanout path.... these differ from normal flops as they have that additional mux that chooses test/func mode. This is given by DFT people..am I correct until here? .so my doubt basically is only flops present in scan chain have that extra mux logic? and there is only one such scannable path per design?
@@VLSIAcademyhub it really helps . thank you very much