LATCH-UP IN CMOS CIRCUITS

[@amitraj-mn4ws]

short and sweet good explanation with example

[@varunjain496]

This explanation was perfect! 10/10. If you would've explained why the i/O voltages go above Vdd and below GND that wouldve been a 11/10

[@girishkanekar5378]

thank you for Sharing the knowledge

[@srilakshmipeteti8087]

Cannot understand any other videos very nice explanation thank you soo much!

[@ashokverma63]

Perfect explanation ❤❤ Thanks a lot 😊

[@tanmaychaudhary5544]

excellent explanation! keep it up

[@Hckr-gs3rx]

Thank you for your effort in bringing the knowledge to us.

[@manasan6839]

Very good Explanation we are expecting more videos on the subject

[@backtobasics5602]

Thanks.. Will be releasing more videos soon.

[@Cristiano_Hindi]

Nice. Thanks

[@Free_Agent_007]

good explanation

[@backtobasics5602]

Thank you.

[@vijayshreeadhikari3989]

Amazing explanation ma'am

[@stewie6520]

Thanks for the clear explanation

[@aniruddhmallya3282]

Gr8 explanation!

[@rammutyala3419]

Madam plz explain about endcap cells and filler cell difference .exact difference with clear . plzzzzzzzzzzzz

[@ganeshgani263]

I have a doubt on it ,here both npn and pnp transistor are forming but in any transistor will activate by base region ,in above you are explained with emitter and base both are in same voltages and there is no conventional current at base region then who can transistor will on

[@eldonjakeenerio8634]

Thanks!

[@AmitKumar-rv9ys]

This is latched up ...so this is called as latch up :)

[@KarineGrigoryan-ob7gq]

I think there is mistake of connection of diode between VDD and n-well. Shouldn’t that diode connected to input instead of VDD?

[@Free_Agent_007]

can you do on video how can we prevent latch-up

[@backtobasics5602]

Okay.. Will try to make a video on this topic.

[@Free_Agent_007]

Your voice is so clear to understand. Keep up good work.

[@backtobasics5602]

Thanks.

[@rammutyala3419]

Increasing the well area and decreasing the resistance

[@ishanagarwal680]

Plssss explain, why the circuit becomes vicious and clamping and clipping in little bit more detail......

[@harikrishna-cc4qg]

How input or output >VDD/

[@backtobasics5602]

Due to disturbances , VDD experiences voltage droop and ground experiences ground bounce.

[@anilsn8219]

what makes the input or output to be more than vdd or less than gnd?

[@ignaciodelgado889]

Voltage injected through other nets due to coupling capacitance.

[@nephewniece3312]

How many diods & transistors will form in cmos?

[@karthiksrinivas54]

Can you suggest books from where you learn these concepts , especially on Physical cells

[@backtobasics5602]

I did not find any book on physical cells. I have learnt it from internet and seeing the layout practically.

[@artiwagh5090]

This is dc and transient analysis

[@UmairuddinAshraf]

1:34

[@BITSIAN23]

Not clear

[@AyushGupta29164]

mam hindi bol lo

[@calypso8883]

She is explaining like a blind news reporter. Wasted my time. This is the true face of Indian education system.