00:02 Understanding Well Tap Cell as a remedy for CMOS latch-up issue 00:35 CMOS latch-up can cause power to ground short. 01:10 Parasitic elements in PNP and NPN transistors 01:46 Substrate and well resistance in VLSI 02:22 Current flows through the emitter terminal when tapped, bypassing high-resistance 02:55 Importance of good tap in VLSI design 03:28 A Shorter standard cell with a separate capsule was introduced for tapping 04:04 Standard cells are designed with tapless nodes to avoid CMOS latch-up.
But still there exists latchup by connecting the body terminals to vdd/gnd right , because of high resistance path. For this, The tap cells are made of high concentration than the std cells in order to provide a low resistance path to avoid latchup is it right sir
Only one well tap cell in a row should be enough right ? , since all the std cells in a row are connected then ,Why multiple well tap are required to be placed in a row?
@@VLSIAcademyhub is there any reference book or any material where I can get such conceptual understanding of chip level techniques. Because the above question which I asked is not explained in any of UA-cam channels Thanks for that answer, but in which book I can find such concepts,can you please tell me
00:02 Understanding Well Tap Cell as a remedy for CMOS latch-up issue
00:35 CMOS latch-up can cause power to ground short.
01:10 Parasitic elements in PNP and NPN transistors
01:46 Substrate and well resistance in VLSI
02:22 Current flows through the emitter terminal when tapped, bypassing high-resistance
02:55 Importance of good tap in VLSI design
03:28 A Shorter standard cell with a separate capsule was introduced for tapping
04:04 Standard cells are designed with tapless nodes to avoid CMOS latch-up.
Thanks alot for timestamps
But still there exists latchup by connecting the body terminals to vdd/gnd right , because of high resistance path.
For this,
The tap cells are made of high concentration than the std cells in order to provide a low resistance path to avoid latchup is it right sir
Hi Sir, appreciate the video..but the cursor is too small, maybe you can consider make it bigger.
Anyway thanks for the videos.
Thanks King Julian.
How does the tap cell lower the resistance value of the substrate?
i think you have connected source of N channel FET with Vdd ?. or perhaps source and drain are changeable.
Actually drain and source are interchangeable but output must be connected to drain
Thank you sir for clear explanation
@@VLSIAcademyhub Sure Sir, definitely
Only one well tap cell in a row should be enough right ? , since all the std cells in a row are connected then ,Why multiple well tap are required to be placed in a row?
@@VLSIAcademyhub is there any reference book or any material where I can get such conceptual understanding of chip level techniques.
Because the above question which I asked is not explained in any of UA-cam channels
Thanks for that answer, but in which book I can find such concepts,can you please tell me
NO, with a 60-micron space in a row, we can place well-tap cells, checkerboard fashion we will place.
After tapping,Rsub comes in parallel with which resistance??
I think emitter resistance.
Super...
,♥️❣️