Hi Ravi, Yes the phase noise for a ring based oscillator can vary between -85 to -90 dBc/Hz,which is more high compared to a LC based oscillator that can give a better phase noise value ranging from -105 to -130dBc/Hz. You can improve the phase noise by adding filters to your supply or can maybe do current starving techniques. There are a lot of IEEE papers that are there for improving phase noise. I would suggest you to go thru some IEEE papers that give you some effective solutions.
thank you, here is a forum, that explains, you can use auto calculate community.cadence.com/cadence_technology_forums/f/custom-ic-design/2661/beat-frequency-in-spectrerf-pss-simulation
Hi Niranjan, I am using Tanner(T-spice) tool for Ring Osc but unfortunately its not showing me proper waveform of it, Do you also work upon Tanner tool?
hello! i am working on current starved vco ,using LT spice free version,how do i figure out the phase noise ,and i also hspice v-2008 free,cscope file is not there,please help me
Hey I am working on PSS and Pnoise analyses for a ring oscillator. In your example you mention that the phase noise is quite high for the design, what would be the optimum value of phase noise. Could you give me some pointers on reducing the phase noise of a ring oscillator. I am working on 45nm technology.
Wijdane Am : the simulator will not know the initial condition for a ring oscillator. You have to force a net to a voltage to start. For a ring oscillator vco you need current starving technique to change the frequency
Alternatively you can force a voltage level(convergence aids) without a VPWL, on a net at t=0 to kick start the oscillator. Otherwise on simulator you cannot start oscillator.
Hi Sudipta , wow its been ages since i worked onto cadence. Please see below post for more info. community.cadence.com/cadence_technology_forums/f/custom-ic-design/41581/error-sfe-874-unexpected-end-of-line-while-running-a-scs-file-generated-using-ade-l-cadence-virtuoso-v6-1-4-with-spectre
Hi Ravi,
Yes the phase noise for a ring based oscillator can vary between -85 to -90 dBc/Hz,which is more high compared to a LC based oscillator that can give a better phase noise value ranging from -105 to -130dBc/Hz. You can improve the phase noise by adding filters to your supply or can maybe do current starving techniques. There are a lot of IEEE papers that are there for improving phase noise. I would suggest you to go thru some IEEE papers that give you some effective solutions.
thanks for this useful video....can you please tell me that, how to choose beat frequency? thanks once again.
thank you, here is a forum, that explains, you can use auto calculate
community.cadence.com/cadence_technology_forums/f/custom-ic-design/2661/beat-frequency-in-spectrerf-pss-simulation
Nice work Niranjan
Why do we calculate frequency vs time plot in a VCO?
Very nice video, thanks a lot!
Tnx for sharing this video with us.
Hi Niranjan,
I am using Tanner(T-spice) tool for Ring Osc but unfortunately its not showing me proper waveform of it, Do you also work upon Tanner tool?
Thanks for the informative video
How to plot waveform of phase noise
hello!
i am working on current starved vco ,using LT spice free version,how do i figure out the phase noise ,and i also hspice v-2008 free,cscope file is not there,please help me
Hey I am working on PSS and Pnoise analyses for a ring oscillator. In your example you mention that the phase noise is quite high for the design, what would be the optimum value of phase noise. Could you give me some pointers on reducing the phase noise of a ring oscillator. I am working on 45nm technology.
around -80 dBc to -130 dB
You put a Vpwl it's normal to get oscillation!! so where is the interest of VCO??
Wijdane Am : the simulator will not know the initial condition for a ring oscillator. You have to force a net to a voltage to start. For a ring oscillator vco you need current starving technique to change the frequency
Alternatively you can force a voltage level(convergence aids) without a VPWL, on a net at t=0 to kick start the oscillator. Otherwise on simulator you cannot start oscillator.
thanks :)
while simulate i face :"ERROR (SFE-874): "input.scs" 31: Unexpected end of line" this problem. could you help me how to solve it.
Hi Sudipta , wow its been ages since i worked onto cadence.
Please see below post for more info.
community.cadence.com/cadence_technology_forums/f/custom-ic-design/41581/error-sfe-874-unexpected-end-of-line-while-running-a-scs-file-generated-using-ade-l-cadence-virtuoso-v6-1-4-with-spectre
17:09
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