AMS - Verilog code in cadence - [ part 1]

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  • Опубліковано 5 січ 2025

КОМЕНТАРІ • 11

  • @abhishekpandya283
    @abhishekpandya283 2 роки тому

    Hello Sir, How do I have multiple pins for the ports like "input [3:0] a", for this kind of structure it shows only one pin. I want 4 pins for this as it should be in Verilog.
    Let's say for the entire processor(32 bits), we can't write individual ports!!!

  • @trunganhnguyenthanh2768
    @trunganhnguyenthanh2768 4 роки тому +2

    Hello when I create a verilog model it shows me the following error:
    "cannot find ncvlog executable from your path"
    How do i fix it? Thanks

    • @jtb016
      @jtb016 2 роки тому

      did u find a fix

  • @shubhamkhanna7910
    @shubhamkhanna7910 4 роки тому

    @Hussein create Symbol popup is not coming...pls help

  • @Z_ahri
    @Z_ahri 2 роки тому

    @Hussein Hussein i want library connectLib ??

  • @marychristina8016
    @marychristina8016 4 роки тому

    What to do if I want to instantiate one code into another? Eg: I have the verilog code for both full adder and ripple carry adder using full adder. How to implement this?

    • @hessiunmohamed24
      @hessiunmohamed24  4 роки тому

      It should be very simple, you just need to create the block of the full adder (FA) and simply use it as many times as you need to create the ripple carry adder

  • @chinmayeramamurthy4302
    @chinmayeramamurthy4302 5 років тому

    I am trying the same steps for D-FF but it just does not seem to work. The input itself is displayed incorrect on the waveform window. Can someone help?

    • @hessiunmohamed24
      @hessiunmohamed24  5 років тому

      what is the type of the input source that you are using? ( Vpulse, Vsin, ...)

  • @qemmm11
    @qemmm11 Рік тому

    Creat Symbol (NOT)??
    It loos like Dxdesigner (viewdraw )schematic Design Rules😊

  • @su61712
    @su61712 2 роки тому +1

    Your voice volume is really low