Cadence Tutorial for Ring Oscillator with Parametric sweep/GoldLighT Technologies

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  • Опубліковано 8 жов 2024
  • Synopsys Custom Designer Tutorial for inverter using Parametric sweep using SAE tool
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КОМЕНТАРІ • 8

  • @viratcheruku
    @viratcheruku Рік тому +1

    Can you explain how you have come up with these values for FET sizes, number of stages and capacitor value

    • @voxel9470
      @voxel9470 10 місяців тому

      To find the correct transistor width, you would use a parametric sweep to determine where it's balanced. In this case I'm assuming the # of stages and capacitor values are kind of arbitrary, but calculations for both of those are detailed in section 4.5 of the textbook CMOS VLSI Design A Circuits and Systems Perspective, 4th Edition

  • @azaira010
    @azaira010 3 роки тому

    Thank you very much....helpful video

  • @sharonpaul2824
    @sharonpaul2824 2 роки тому

    Thanks a ton!

  • @sudiptachakraborty5836
    @sudiptachakraborty5836 2 роки тому

    while simulate i face :"ERROR (SFE-874): "input.scs" 31: Unexpected end of line" this problem. could you help me how to solve it.

  • @Krishna-ei5pw
    @Krishna-ei5pw 3 роки тому

    Hii goldlight

  • @mohsenrazzaghi3880
    @mohsenrazzaghi3880 3 роки тому +2

    This video could have been waaaay shorter!!!
    24 minutes? seriously?

    • @nil7208
      @nil7208 4 місяці тому

      shut up ungrateful dog