Layout design and post layout simulation in Spectre

This tutorial video covers the basics of layout design and post-layout simulation using Cadence Spectre. The demonstration is done for a CMOS inverter in UMC 180nm technology. Calibre tool has been used for the DRC, LVS and parasitic extraction. The video will be helpful for the beginners of analog circuit design.

[@nikolavulinovic4085]

Great job. People like you make the world go around! Thank you!

[@sagar35756]

That's what I was looking for everywhere. Finally here it is!! Thanks a lot

[@wendypatriciafernandez3869]

Excellent tutorial. Thank you very much for sharing.

[@赵逸飞-q5l]

Very detailed tutorials, Thanks!

[@schmydstify]

Great tutorial! Thank you!

[@bhanprakashgoswami4626]

Thanks a lot. Really useful video.

[@ulagracerosyidah9323]

thanks for the video. im designing a rectifier, which the input AC in modulation. when I do LVS check, it show an error because the PMOS of rectifier is connected to capacitor, not the VDD. do you have any advice? thanks

[@ECEBESTALWAYS]

can you tell me why assura tab not showing in my cadnece....

[@Sennajar1983]

Hi sir,
When i do the RC extraction using PEX .. while loading pex.tec file i get the following error " undefined layer name parameter:NSD_C" can you suggest a method to overcome this error??

[@AmirKhan_KnowTech]

I am not getting the result and the error is "the cell view has been modified since the last extraction error validate"

[@DrNijwmWary]

Yes, this is a common issue. You need to save your schematic.