Design Integration - John Park: Design Challenges for 3D-ICs

Road to Chiplets - Design Integration
Design Challenges for 3D-ICs
John Park
Cadence
Whether you are an ASIC designer or package designer, you can expect several new design and analysis challenges when transitioning from the world of single die architectures to the world of More-than-Moore. 3D integration of these multi-chiplet designs raises even more challenges. This presentation will outline the trends and design challenges related to 3D-IC architectures.