I haven't been in the hardware business since about 1996. In some ways, the changes seem almost trivial; I remember discussions of stacking bare silicon chips, heat dissipation, packaging, interconnects, etc, but we were a board-level company, so it was all just poorly-informed guesswork. These discussions are fascinating in their details.
People will always nod uncritically if they hear, "things are changing faster than ever these days." But in a lot of ways, change is incredibly slow once an industry hits an inflection point where there is a ton of inertia. The really significant changes happening today are all stuff that has been kind of on the radar and baking in labs for decades. In many ways, the 90's was a much more technologically disruptive time than the 2020's.
This is the best tech channel on UA-cam and that's saying some shit because there are tons of them. If I've ever wondered about something in the tech world this guy reads my mind and post the video shortly after. Great job man keep up the good work.
I remember when stacking was putting a RAM box on the side of the big box with the CPU, instead of running fat parallel cables down under the floor, and up into the other box. Going from > 4 meters to half a meter.
Pretty amazing what Ryzen brought out. I'm still running a bulldozer "8" core 8350.. I'm no power user, but damn if ryzen isn't looking pretty great right now.
Embedded parts have been using dram stacked on top of the SoC for many years already. Just less advanced/specialized versions of the same tech. E.g. various smartphones and arm tablets have been using that tech.
Awesome video as always, just a small addition, TSMC 3D stacking don't use micro bumps, they use direct copper bonding. IMHO Intel version is called tiles just for arrogance.
Thank you Asianometry for such a great video on stacking! 11:15 and on, about image sensors... It is worthwhile to mention two dissimilar technologies used in this space: The first one is BSI (Back Side thinned Illumination) which is not stacking. This only applied to each and every active pixel (sensel) per-pixel dedicated region. It's like double-sided printing on a piece of paper. The first side created is the transistor side ( 11:40 picture's bottom side), then the entire wafer is flipped bottom side up, polished (thinned), processed to form the photo diode region (almost 100% fill factor.) AR layers, mosaic filter pigment deposited, and microlenses are grown on that side. Other common functions, shared sensel components, and support logic circuitries were also fabrcated on the first part of the process (on first side), mostly outside of the active pixel region Sony marketed it as EXMOR-R (R reflects BSI design.). Note that at this point, it still is one die per image sensor. SONY later introduced 2-die stacking (bonded using TSVs) marketed as EXMOR-RS. Some support functions are moved to the second die and other new features are also built on this new (mostly) logic-only die such as memory, decision logic, arithmetic ops, I/O, etc. Now it is truly stacking.
I recall Intel made a chip with something like 30 cores where each core had the L2 cache under the individual core, making for pretty exceptional latency. The problem was the things would basically melt, which is seemingly the problem we still have today. Without some kind of magic (MRAM) 3D stacking is probably going to be a serious thermal challenge with SRAM. Maybe not so much with eDRAM. Anywho, great video as usual.
Texas Instruments did cpu-dram stacks back in the early 2010s or earlier already, e.g. in the OMAP series for e.g. smartphones. For example the Omap 3500 series that was used e.g. in the original TI Beagleboard SBC, that had a cortex-8 cpu with a 512MiB Dram chip on top. But it was limited to that one Dram chip of course, and couldn't stack further.
Once again an EXCELLENT long awaited episode about chip stacking! An amazing job as always, no BS just real facts and proper info which in today's world is WORTH of GOLD! (I will become a Patreon, u r on my list). I particularly like the 13:40 part where u highlight very important point about limitation in SRAM/cache shrinking. This is in my opinion a CRUCIAL reason to 3D stack SRAM in a similar way as AMD did with their V-Cache and of course increase its performance and size. I would say and go as far that I would predict that in the next decade not just because of the limitation of the Moore's Law but mainly because of the rise of the in memory brain-like neuromorphic computing we will see stack SRAM rising to GBs which would push classic DDR even further away from the CPU/SOC. Of course implementation of the next gen transistors will play its role too, as well as the further development in silicon photonics which should finally get us out from the limitations in degrading speeds when being further away form the CPU/SOC. Still the key in my opinion is that the most fastest next gen memory like future SRAM we can come up with will be on par with the CPU/SOC and there won't have any limit in speed between them. Von Neumann architecture will be eventually replaced by a new standard where CPU/SOC is not the Alpha&Omega of the computer. We have to simulate our organic brain in a synthetic form which won't degrade and evolve further. This is the main advantage of us humans that we can create something which will surpass us and will last much longer than we do. Just take a look at the OLED panels... everything organic degrades, however synthetic is much more long lasting (microLED). Still the organic creation and its interlinked supersystem is still the most amazing creation above any synthetic form we will come up with in the future and we should never forget that. But maybe a way forward is that we understand them both as one can inspire the other and help us along the way to grow as a species.
AMD had to add substrates to their Vcache CPUs (5800X3D, 7800X3D, etc....) to make an EVEN HEIGHT across the top of the package. The stacked cache only covers the cache on the main IC, so there's a lot of space that isn't covered by the stacked cache. In the diagram you show at the very end, the added substrates sit over the cores. But you need the top of the package to be the same height (Z-height) because you need a VERY level top surface of the IC, because you put a heat spreader on top of this die and there has to be full contact between the IC and the heat spreader. On top of the heat spreader, which covers the entire package and is what you look at when you see the top of a CPU, you put thermal paste and then a cooler which wicks heat away from the CPU. So those substrates exist to make an even height to the IC so the complete IC package is in full contact with the heat spreader. And TSMC's die stacking has been in mass production since early 2022 when AMD's 5800X3D was released. It's now in 3 more AMD CPUs, their new 7800X3D which came out today, the 7900X3D and the 7950X3D. Or, these are the desktop CPUs. AMD also has server parts with stacked cache going back to Zen 3 EPYC, so once again early 2022. You didn't cover the limitations of stacking, heat. For CPUs or GPUs stacking is very limited because stacking a die over die when that die contains CPU cores which clock VERY fast, heat becomes an issue. If the cores are on the bottom stack, the heat from the cores has to pass up through another layer of transistors, and this will make that top layer EXTREMELY hot. So, stacking is limited, and best suited for circuits which are clocked slower meaning less power consumption meaning less heat. Heat dissipation is everything with these packaging technologies.
No they are not. How dare you? Who do you think you are? Nobody knows anything about that. You can not possibly know anything. WTF IS WRONG WITH YOU OMG
Hi Jon, please consider a video series on the OSAT companies. You mentioned a few, Amkor, ASE, UMC these are very interesting "hidden champions" that are critical to modern hardware.
very informative, I am here to understand you guys to see how I can help in adhesives, thermal insulation, sealants, and coatings of your components, really very informative, thank you.
Sony uses stacked image sensors so the transistors are on a layer below the photodiodes maximizing their size. Certain chips also include a cache used for global shutter or 960hz video framrate for 0.2 seconds.
I suspect one of the viewers might know this. Do large sizes of L3 SRAM get as hot as the compute or accelerate portions of the die or is it essentially the same even if on a single planar wafer? Curious if the delta T for the cache is significantly lower then possibly it-itself could act as part of the heat transfer package to a heat spreader and to outside world.
The OG 3D CPU was the Cray 2 Supercomputer, where the CPU was built from a tightly packed stack of logic boards. The big disadvantage of that tight packing was that it had to be submerged in an inert cooling liquid.
Sony is also stacking its CMOS image sensors on ADC (analog-to-digital converter) and DRAM for much better readout speeds. -- I realized you actually got into it when I continued with the video lol
The chip industry differentiating 2.5D vs 3D per the examples you researched is arguably a semantic play. The examples all look like stacked 2Ds to me. True 3D is substantially more difficult than any ever-more-intricate layering of flat objects. As soon as the word “stacking” is used, that is not going to be true 3D. An analogy exists in the CAD and data visualization market. AutoCAD and ArcGIS use (do they still?) data interpolation in 2D and then stack the solutions into a “3D” image or matrix, generating a 2.5D result that looks 3D, but is not truly. Ctech EVS does true 3D data interpolation. Making a computer chip that is genuinely 3D might require light to flip bits, and detect the flip (w diff wavelength), in a translucent matrix.
3D with layers is still 3D. You're right that if we could have the device density be the same in each direction it would be much more compact. Heat removal will always be an issue though, so flattened shapes will probably stick around.
Please, address final product failure rates in relation to time. Shall we expect more computer failures with decreasing size and increasing complexity. What sort of devices might be more likely to fail and why?
I’m glad you were on Moore’s Law Is Dead, been an avid deer listener ever since! I recently built a new PC around around the 7950X3D and am excited to see where we are at in 10 or 20 years.
As for the overcoming fundamental limits which industry is about to hit, there is a third approach: new materials and superlattices, potentially allowing higher frequencies and lower power consumption. (Like GaAs-based structures).
My assignment was to make low powered version of these chips. We use (i dont remember the gates) but it turns out to be way bigger than the original chip design. Good times 😅
I found MCMs really frustrating. Customers would ask for huge numbers of something we didn't have, but which was a simple combination of 2 or 3 things we did have. So, do an MCM with the existing dies and we have a quick turnaround solution. However, when we got to the grubby details these things hardly ever worked out.
At 11:35 you said "for their part, the memory industry went three dimensional back in the early 2010s", while showing a picture of a 3D NAND chip. The 3D NAND chip you're showing does not use die stacking. The 3D part of 3D NAND refers to multiple layers of memory cells built on top of the surface of the silicon, as opposed to "planar" memory cells or transitional transistors, which are only built one layer, directly on the silicon surface. The 3D NAND chips are still monolithic chips - single silicon dies, with many layers of NAND storage cells. Those 3D dies can then be stacked into multi-chip-packages using traditional die-stacking and wire bonding techniques, of course, but like you said at the beginning, that's been going on for decades.
Had the same idea. SRAM can also be much more dense when it's made with a process optimized for it, which can be used when it doesn't need to share a die with logic.
It's interesting why they put L3 cache on top. The CPU die is hotter, you would want *it* to be closer to the heatsink. Probably because current CPU die is designed so that it can't interface with L3 _under_ it, the contacts are on the top, not bottom.
50 years in and we are still only making sandwiches. 1. Curl the chip into the form of a cylindrical tube. Yes they can be manufactured that way, but it requires capital. Why? because you can pump cooling through the tube and contacts and leads can radiate outward to other components. 2. Design the computer in a laminar way with other components on the outside of the central core. This is kind of biomimicry in a way. Like how a living plant or circulatory system distributes nutrients to surrounding cells. 3. Have memory surrounding the central processing tube (cpu). 4. Have graphics chips in line with the central processing tube. The graphics chips have also been formed into a tube as well. 5. Use evaporative cooling...an inert fluid that can even bubble in the central hollow of the chip and lift the heat up and away as it is created. 6. Shorten the distances traces from the chips have to go by having them radiate outward in successive layers. 7. Use less voltage and have a higher thruput of coolant. This makes the system have built in short cuts as well as built in cooling channels, as well as a less urban sprawl kind of structure and mirrors the efficiency and simplicity of design seen in living systems. Mother nature outgrew making simple sandwiches early on. Mother nature got tubular. Thank you, my fellow tube-based organisms for reading all of this.
Is it possible to just fabricate them on the wafer in 3D just logic obviously. Or is it just to damaging to the yield? Probably thats the reason we use packaging right?
🎯 Key points for quick navigation: 00:03 *📦 Introduction and Definitions* - Introduction to die stacking and its importance following Moore’s Law. - Definitions and distinctions between 2.5D and 3D packaging. 01:25 *❓ Necessity of Advanced Packaging* - Discussion on the necessity of advanced packaging technologies due to the end of Moore's Law. - Introduction to accelerator chips alongside CPUs and the Chiplet approach. 02:24 *🕰️ History of 2.5D Integration* - Overview of the history and development of hybrid circuits and multichip modules (MCMs). - Explanation of how these historical technologies laid the groundwork for modern 2.5D integration. 04:16 *🌉 2.5D Integration and TSV* - Introduction to Through-Silicon Vias (TSVs) and 2.5D integration. - Key technological advancements and first commercial implementations involving TSVs. 05:40 *⚙️ Advantages and Challenges of 2.5D* - Advantages of 2.5D integration in terms of physical space, thermal limitations, and memory capacity. - Discussion on disadvantages such as cost and points of failure, and potential future improvements. 07:08 *🔧 Chiplets and Standards* - Recent developments in chiplet technology and industry standards. - Potential geopolitical implications and the adoption of chiplet technology. 08:34 *🏛️ 3D Integration History* - Historical background of 3D integration dating back to the 1950s. - Introduction to Tinkertoy circuits, Micro-Modules, and early attempts at vertical stacking. 09:31 *📱 Package on Package* - Development and examples of Package on Package solutions. - Explanation of their adoption in consumer electronics like smartphones. 11:00 *🏢 Die-to-Die Stacking* - Explanation of Die-to-Die 3D integration via wire bonding and TSVs. - Comparison of traditional wire bonding versus TSV potential. 11:29 *📸 Stacked Image Sensors* - Introduction to the use of TSVs in CMOS image sensors and their benefits. - Industry breakthroughs and production timelines for stacked image sensors. 12:26 *🔍 Overcoming Manufacturing Challenges* - Major manufacturing challenges faced in 3D stacking. - Solutions like cooling techniques, defect testing, and reliability measures. 13:21 *💡 Conclusion* - Latest advancements in 3D die stacking in key products and companies. - Summary of TSMC’s recent achievements and market readiness for deep chiplet-style integration. Made with HARPA AI
Can someone explain why we need to stack separate chips, instead of just adding more layers to the same chip? I know different memory and compute use different processes but can you really not just move the wafer from one to another?
They do that in DRAM and flash memory chips. I'm not sure why you don't see it done with logic. My guess is the transistors you can make are lower performing and slower so the processor would slower.
@@vitormoreno1244 the V- cache chip is SRAM, and they are usually made on the same process as logic, because in every processor except some of AMD's new ones, the cache is on the same chip as the logic. Making a chiplet with only SRAM let them optimize for it and double the density that they otherwise would get for the process.
@@davidgunther8428 I'm pretty sure it's also because AMD were alerted by TSMC that memory-size scaling is going to slow down first - recall in the video when Asianometry mentions that memory only shrunk by 5% between 4nm and 3nm? Apparently 3nm+ will have NO shrinking of memory structures. It then behooves AMD to dislodge their cache from their logic, for future processors. (same obviously why they did the same with GPU's starting with the 7000-series, but without 3D-stacking)
If we are to keep 3D stacking, the chips will need to start having internal capillary cooling systems to pull heat away from the chips and onto its packaging to prevent serious thermal throttling.
This channel has been en fuego so far this year. These videos are a clear as, and as efficient as, the video classes on semiconductor technology and processes at Motorola University. However, because they cover developments and feature images from a wide variety of vendors and sources, they are far more catholic in their breadth of knowledge. Terrific work!
That ".5 more 'D'" might be neat, but, maybe I should listen to the presentation again to try to better comprehend what is "D" and what is the other 2.5 of it.
D means "dimension" 2D is flat surface 3D means volume 2.5D here are chips where parts (compute/cache) aren't on top of each other, but there's a layer of vertical+horizontal wires below
The channel is too focused on CPU/GPU. Image sensors were the driver for 3D stacking. Direct wafer bonding (with Cu to Cu direct connects) of the pixel sensor chip to the image sensor processor is in high volume mass production since years. Everybody has such product today. The technology is amazing the pixel sensor wafer is in the end only 10um thick and processed from both side with just tens nm overlay shift. Also the wafer to wafer overlay shift much less than 1um. Todays smartphone cameras rely on that technology. You have very small pixels for small/cheap chips with many pixels but still low noise.
I haven't been in the hardware business since about 1996. In some ways, the changes seem almost trivial; I remember discussions of stacking bare silicon chips, heat dissipation, packaging, interconnects, etc, but we were a board-level company, so it was all just poorly-informed guesswork. These discussions are fascinating in their details.
3 months ago? 'FIRST' commenters never had a chance
I haven't been a poorly-informed business since about 1996. I remember these discussions, in some ways. We were stacking bare silicon chips.
3 months wtf
People will always nod uncritically if they hear, "things are changing faster than ever these days." But in a lot of ways, change is incredibly slow once an industry hits an inflection point where there is a ton of inertia. The really significant changes happening today are all stuff that has been kind of on the radar and baking in labs for decades. In many ways, the 90's was a much more technologically disruptive time than the 2020's.
@@guaposneeze People will always nod uncritically in a lot of ways. In many ways faster than ever these days the changes happening today.
The Royal Society for Putting Things on Top of Other Things approves.
This is the best tech channel on UA-cam and that's saying some shit because there are tons of them. If I've ever wondered about something in the tech world this guy reads my mind and post the video shortly after. Great job man keep up the good work.
This is the shit tech channel on UA-cam. This guy reads my mind while I shit and posts a video shortly after.
I remember when stacking was putting a RAM box on the side of the big box with the CPU, instead of running fat parallel cables down under the floor, and up into the other box. Going from > 4 meters to half a meter.
The funniest jokes are the visual ones that aren't verbally acknowledged.
Yesterday I ordered my first 3D stacked techbology - the Ryzen 7800X3D. I am exited since it is my first upgrade in over a decade.
I am also excited for my first 3D stacked technology, 5800X3D. Hopefully, will get it soon. These 3D chips are legendary.
Pretty amazing what Ryzen brought out. I'm still running a bulldozer "8" core 8350.. I'm no power user, but damn if ryzen isn't looking pretty great right now.
@@mikafoxx2717 - that upgrade would blow your mind my fellow fopsoh ;-)
Embedded parts have been using dram stacked on top of the SoC for many years already. Just less advanced/specialized versions of the same tech. E.g. various smartphones and arm tablets have been using that tech.
@@imrevadasz1086 that's not even remotely the same thing. Different memory technology, different rationale, different bonding method.
Awesome video as always, just a small addition, TSMC 3D stacking don't use micro bumps, they use direct copper bonding. IMHO Intel version is called tiles just for arrogance.
Intels 3D stacking is called Ferveros. EMIB is referred to tiles which is 2D.
Thanks for the info!
Thank you Asianometry for such a great video on stacking!
11:15 and on, about image sensors...
It is worthwhile to mention two dissimilar technologies used in this space:
The first one is BSI (Back Side thinned Illumination) which is not stacking. This only applied to each and every active pixel (sensel) per-pixel dedicated region. It's like double-sided printing on a piece of paper. The first side created is the transistor side ( 11:40 picture's bottom side), then the entire wafer is flipped bottom side up, polished (thinned), processed to form the photo diode region (almost 100% fill factor.) AR layers, mosaic filter pigment deposited, and microlenses are grown on that side.
Other common functions, shared sensel components, and support logic circuitries were also fabrcated on the first part of the process (on first side), mostly outside of the active pixel region Sony marketed it as EXMOR-R (R reflects BSI design.). Note that at this point, it still is one die per image sensor.
SONY later introduced 2-die stacking (bonded using TSVs) marketed as EXMOR-RS. Some support functions are moved to the second die and other new features are also built on this new (mostly) logic-only die such as memory, decision logic, arithmetic ops, I/O, etc. Now it is truly stacking.
it is mind-boggling the number of skills and knowledge of those who make such things, and it saddens me when I see some of them getting too old.
Great video, really enjoy your in-depth view
I recall Intel made a chip with something like 30 cores where each core had the L2 cache under the individual core, making for pretty exceptional latency. The problem was the things would basically melt, which is seemingly the problem we still have today. Without some kind of magic (MRAM) 3D stacking is probably going to be a serious thermal challenge with SRAM. Maybe not so much with eDRAM. Anywho, great video as usual.
Texas Instruments did cpu-dram stacks back in the early 2010s or earlier already, e.g. in the OMAP series for e.g. smartphones. For example the Omap 3500 series that was used e.g. in the original TI Beagleboard SBC, that had a cortex-8 cpu with a 512MiB Dram chip on top. But it was limited to that one Dram chip of course, and couldn't stack further.
Once again an EXCELLENT long awaited episode about chip stacking! An amazing job as always, no BS just real facts and proper info which in today's world is WORTH of GOLD! (I will become a Patreon, u r on my list).
I particularly like the 13:40 part where u highlight very important point about limitation in SRAM/cache shrinking. This is in my opinion a CRUCIAL reason to 3D stack SRAM in a similar way as AMD did with their V-Cache and of course increase its performance and size.
I would say and go as far that I would predict that in the next decade not just because of the limitation of the Moore's Law but mainly because of the rise of the in memory brain-like neuromorphic computing we will see stack SRAM rising to GBs which would push classic DDR even further away from the CPU/SOC. Of course implementation of the next gen transistors will play its role too, as well as the further development in silicon photonics which should finally get us out from the limitations in degrading speeds when being further away form the CPU/SOC.
Still the key in my opinion is that the most fastest next gen memory like future SRAM we can come up with will be on par with the CPU/SOC and there won't have any limit in speed between them. Von Neumann architecture will be eventually replaced by a new standard where CPU/SOC is not the Alpha&Omega of the computer.
We have to simulate our organic brain in a synthetic form which won't degrade and evolve further. This is the main advantage of us humans that we can create something which will surpass us and will last much longer than we do. Just take a look at the OLED panels... everything organic degrades, however synthetic is much more long lasting (microLED).
Still the organic creation and its interlinked supersystem is still the most amazing creation above any synthetic form we will come up with in the future and we should never forget that. But maybe a way forward is that we understand them both as one can inspire the other and help us along the way to grow as a species.
Did you hear of generative pre-trained transformers?
AMD had to add substrates to their Vcache CPUs (5800X3D, 7800X3D, etc....) to make an EVEN HEIGHT across the top of the package. The stacked cache only covers the cache on the main IC, so there's a lot of space that isn't covered by the stacked cache. In the diagram you show at the very end, the added substrates sit over the cores. But you need the top of the package to be the same height (Z-height) because you need a VERY level top surface of the IC, because you put a heat spreader on top of this die and there has to be full contact between the IC and the heat spreader. On top of the heat spreader, which covers the entire package and is what you look at when you see the top of a CPU, you put thermal paste and then a cooler which wicks heat away from the CPU.
So those substrates exist to make an even height to the IC so the complete IC package is in full contact with the heat spreader.
And TSMC's die stacking has been in mass production since early 2022 when AMD's 5800X3D was released. It's now in 3 more AMD CPUs, their new 7800X3D which came out today, the 7900X3D and the 7950X3D. Or, these are the desktop CPUs. AMD also has server parts with stacked cache going back to Zen 3 EPYC, so once again early 2022.
You didn't cover the limitations of stacking, heat. For CPUs or GPUs stacking is very limited because stacking a die over die when that die contains CPU cores which clock VERY fast, heat becomes an issue. If the cores are on the bottom stack, the heat from the cores has to pass up through another layer of transistors, and this will make that top layer EXTREMELY hot. So, stacking is limited, and best suited for circuits which are clocked slower meaning less power consumption meaning less heat. Heat dissipation is everything with these packaging technologies.
This is a bot...
Thank you for not using stock clips in this video, I personally like it better with just slides 👍
My man almost at that half a milli I tell you what your stacking? Them views and subs! Let’s goo
3D-stacked variants are already out for Zen 4 as well.
No they are not. How dare you? Who do you think you are? Nobody knows anything about that. You can not possibly know anything. WTF IS WRONG WITH YOU OMG
Hi Jon, please consider a video series on the OSAT companies. You mentioned a few, Amkor, ASE, UMC these are very interesting "hidden champions" that are critical to modern hardware.
very informative, I am here to understand you guys to see how I can help in adhesives, thermal insulation, sealants, and coatings of your components, really very informative, thank you.
Superb video as always. Excellent summation in easy to understand terms.
Folks, share this far and wide. It’s too good not to!
When is your Moore's Law is Dead podcast coming out? I can't wait to listen to it.
ua-cam.com/video/p1m0pc5TkNw/v-deo.html
Unless it’s a more recent one the last one he did was ep. 167 to my knowledge
@@Flameancer found it
ua-cam.com/video/p1m0pc5TkNw/v-deo.html
@@Flameancer He hasn't, but I can see about him coming back on around a year after that episode.
Sony uses stacked image sensors so the transistors are on a layer below the photodiodes maximizing their size. Certain chips also include a cache used for global shutter or 960hz video framrate for 0.2 seconds.
I wonder whether there will be a video about yangtze memory technologies :) I will be excited to see one
That timing though (I have an essay next week exactly about Moore's law being dead and ways to counter it)
Brought to you by, "The Royal Society for Putting Things on Top of Things."
When I start stacking dies, the DM tells me to stop playing around and roll initiative!
I enjoy your presentations.
Wish you would've used the WKUK trenchcoat sketch for that first pic.
love the humour and educational video. Thanks.
9:33 something clicked in my head when i saw polish on the device lol
When will we get cooling channels in between the layers?
Oh, I misread the headline as „stacking has died“ - and was pleasantly surprised to hear it hasn‘t ;-)
At 3:50 UNISYS was formed in 1986 from Sperry and Burroughs - must have been one of those - about packing delay.
I suspect one of the viewers might know this. Do large sizes of L3 SRAM get as hot as the compute or accelerate portions of the die or is it essentially the same even if on a single planar wafer? Curious if the delta T for the cache is significantly lower then possibly it-itself could act as part of the heat transfer package to a heat spreader and to outside world.
The OG 3D CPU was the Cray 2 Supercomputer, where the CPU was built from a tightly packed stack of logic boards. The big disadvantage of that tight packing was that it had to be submerged in an inert cooling liquid.
Sony is also stacking its CMOS image sensors on ADC (analog-to-digital converter) and DRAM for much better readout speeds.
-- I realized you actually got into it when I continued with the video lol
I'm not a programmer or engineer my work has nothing to do with anything technology based but I love your videos. Keep up the great work
"0.5 more D"
Lol, "that's what she said"
"we've been stacking things since the stone age" 😂 earned my like
The chip industry differentiating 2.5D vs 3D per the examples you researched is arguably a semantic play. The examples all look like stacked 2Ds to me. True 3D is substantially more difficult than any ever-more-intricate layering of flat objects. As soon as the word “stacking” is used, that is not going to be true 3D.
An analogy exists in the CAD and data visualization market. AutoCAD and ArcGIS use (do they still?) data interpolation in 2D and then stack the solutions into a “3D” image or matrix, generating a 2.5D result that looks 3D, but is not truly. Ctech EVS does true 3D data interpolation.
Making a computer chip that is genuinely 3D might require light to flip bits, and detect the flip (w diff wavelength), in a translucent matrix.
you sound as if no 3D printer uses layers xD
or that those don't count as 3D either
3D with layers is still 3D. You're right that if we could have the device density be the same in each direction it would be much more compact.
Heat removal will always be an issue though, so flattened shapes will probably stick around.
why does the diagram at 13:10 say SnPb? wasn't all lead removed from electronics solder ages ago for rhos compliance?
Please, address final product failure rates in relation to time. Shall we expect more computer failures with decreasing size and increasing complexity. What sort of devices might be more likely to fail and why?
What's the podcast on moores law is dead? Couldn't find it
FASCINATING
Most informative. 👍🏼👍🏼
wait when was the moors law is dead podcast ?
did i miss it ?
Wait, Blaupunkt, the car audio company from the early 90s made chips?
I’m glad you were on Moore’s Law Is Dead, been an avid deer listener ever since! I recently built a new PC around around the 7950X3D and am excited to see where we are at in 10 or 20 years.
I like Moore's Law is dead too. It didn't make me any better at hunting deer though 🦌
Wait he was on Moore's law is dead?!! When?? I can't find it but would love to hear it
@@Cameronmid1 Episode 167 Broken Silicon
@@JBrinx18 thanks dude!
As for the overcoming fundamental limits which industry is about to hit, there is a third approach: new materials and superlattices, potentially allowing higher frequencies and lower power consumption. (Like GaAs-based structures).
9:32
pole sees polish text
neuron activation
What does it mean to be a chiplet design? Are different chips manufactured on different wafers at different nanometer and "soldered" on?
My assignment was to make low powered version of these chips. We use (i dont remember the gates) but it turns out to be way bigger than the original chip design. Good times 😅
wow! wow! 14:00 they throw'en up some signs bro!
I found MCMs really frustrating. Customers would ask for huge numbers of something we didn't have, but which was a simple combination of 2 or 3 things we did have. So, do an MCM with the existing dies and we have a quick turnaround solution. However, when we got to the grubby details these things hardly ever worked out.
It's a shame you couldn't go into further detail about how they are attacking the issues in the modern chip designs.
Link to the podcast?
Cue the "Perfectly f***ing vertical" meme.
wonder if those 2 kids managed to get some booze
The interconnect seems like a reliability issue to figure out.
At 11:35 you said "for their part, the memory industry went three dimensional back in the early 2010s", while showing a picture of a 3D NAND chip.
The 3D NAND chip you're showing does not use die stacking. The 3D part of 3D NAND refers to multiple layers of memory cells built on top of the surface of the silicon, as opposed to "planar" memory cells or transitional transistors, which are only built one layer, directly on the silicon surface. The 3D NAND chips are still monolithic chips - single silicon dies, with many layers of NAND storage cells. Those 3D dies can then be stacked into multi-chip-packages using traditional die-stacking and wire bonding techniques, of course, but like you said at the beginning, that's been going on for decades.
i typically don't catch the actual podcast, just his produced video. moore's law is dead is dope. and you rule. i'll have to listen to that one
I had no idea you went to Moore's Law Is Dead
Steve Jobs said to engineers: Die2die or die
What can you say about durability, long lifespan of Power management IC units in Chiplet
When will we get 2nm with chiplet packaging
This all sounds like multi-layer boards shrunk down to chip size dimensions. PTH (Plated Through Holes) instead of TSVs.
That intro :))
since they hit the barrier this is the only option to ,make improvements ???
Is the title of the video a Star Trek reference?
Ackchyually! This was a good video, actually. :)
we need L1 cache glued directly above the compute transistors that need it or else its gonna be a big limiting factor.
Had the same idea. SRAM can also be much more dense when it's made with a process optimized for it, which can be used when it doesn't need to share a die with logic.
12:56 not that silicon conducts heat very well...
RIP stacking, you will be missed.
It's interesting why they put L3 cache on top. The CPU die is hotter, you would want *it* to be closer to the heatsink.
Probably because current CPU die is designed so that it can't interface with L3 _under_ it, the contacts are on the top, not bottom.
1:06 the Dimension Integer Authority…
moore's law was never about performance, it was always about transistors.
A shoutout to “Moore’s Law is Dead” 🙌🏾
50 years in and we are still only making sandwiches.
1. Curl the chip into the form of a cylindrical tube. Yes they can be manufactured that way, but it requires capital. Why? because you can pump cooling through the tube and contacts and leads can radiate outward to other components.
2. Design the computer in a laminar way with other components on the outside of the central core. This is kind of biomimicry in a way. Like how a living plant or circulatory system distributes nutrients to surrounding cells.
3. Have memory surrounding the central processing tube (cpu).
4. Have graphics chips in line with the central processing tube. The graphics chips have also been formed into a tube as well.
5. Use evaporative cooling...an inert fluid that can even bubble in the central hollow of the chip and lift the heat up and away as it is created.
6. Shorten the distances traces from the chips have to go by having them radiate outward in successive layers.
7. Use less voltage and have a higher thruput of coolant.
This makes the system have built in short cuts as well as built in cooling channels, as well as a less urban sprawl kind of structure and mirrors the efficiency and simplicity of design seen in living systems.
Mother nature outgrew making simple sandwiches early on. Mother nature got tubular.
Thank you, my fellow tube-based organisms for reading all of this.
Why cant they make x86 & ARM (risc+cisc) combine??
Warehouse workers top worry - to…die stacking.
Is it possible to just fabricate them on the wafer in 3D just logic obviously. Or is it just to damaging to the yield? Probably thats the reason we use packaging right?
Reminds me of the Raspberry Pi Zero 2 W.
Reminds me a bit about Jenga.
Add Tinkertoy circuits are the one with color on top circuits ❓☺️ look similar
🎯 Key points for quick navigation:
00:03 *📦 Introduction and Definitions*
- Introduction to die stacking and its importance following Moore’s Law.
- Definitions and distinctions between 2.5D and 3D packaging.
01:25 *❓ Necessity of Advanced Packaging*
- Discussion on the necessity of advanced packaging technologies due to the end of Moore's Law.
- Introduction to accelerator chips alongside CPUs and the Chiplet approach.
02:24 *🕰️ History of 2.5D Integration*
- Overview of the history and development of hybrid circuits and multichip modules (MCMs).
- Explanation of how these historical technologies laid the groundwork for modern 2.5D integration.
04:16 *🌉 2.5D Integration and TSV*
- Introduction to Through-Silicon Vias (TSVs) and 2.5D integration.
- Key technological advancements and first commercial implementations involving TSVs.
05:40 *⚙️ Advantages and Challenges of 2.5D*
- Advantages of 2.5D integration in terms of physical space, thermal limitations, and memory capacity.
- Discussion on disadvantages such as cost and points of failure, and potential future improvements.
07:08 *🔧 Chiplets and Standards*
- Recent developments in chiplet technology and industry standards.
- Potential geopolitical implications and the adoption of chiplet technology.
08:34 *🏛️ 3D Integration History*
- Historical background of 3D integration dating back to the 1950s.
- Introduction to Tinkertoy circuits, Micro-Modules, and early attempts at vertical stacking.
09:31 *📱 Package on Package*
- Development and examples of Package on Package solutions.
- Explanation of their adoption in consumer electronics like smartphones.
11:00 *🏢 Die-to-Die Stacking*
- Explanation of Die-to-Die 3D integration via wire bonding and TSVs.
- Comparison of traditional wire bonding versus TSV potential.
11:29 *📸 Stacked Image Sensors*
- Introduction to the use of TSVs in CMOS image sensors and their benefits.
- Industry breakthroughs and production timelines for stacked image sensors.
12:26 *🔍 Overcoming Manufacturing Challenges*
- Major manufacturing challenges faced in 3D stacking.
- Solutions like cooling techniques, defect testing, and reliability measures.
13:21 *💡 Conclusion*
- Latest advancements in 3D die stacking in key products and companies.
- Summary of TSMC’s recent achievements and market readiness for deep chiplet-style integration.
Made with HARPA AI
Can someone explain why we need to stack separate chips, instead of just adding more layers to the same chip? I know different memory and compute use different processes but can you really not just move the wafer from one to another?
They do that in DRAM and flash memory chips. I'm not sure why you don't see it done with logic. My guess is the transistors you can make are lower performing and slower so the processor would slower.
That is because the DRAM process is different from the HPC process, that is why on Zen x3D the stacked cache have double size on the same area.
@@vitormoreno1244 the V- cache chip is SRAM, and they are usually made on the same process as logic, because in every processor except some of AMD's new ones, the cache is on the same chip as the logic. Making a chiplet with only SRAM let them optimize for it and double the density that they otherwise would get for the process.
@@davidgunther8428 I'm pretty sure it's also because AMD were alerted by TSMC that memory-size scaling is going to slow down first - recall in the video when Asianometry mentions that memory only shrunk by 5% between 4nm and 3nm? Apparently 3nm+ will have NO shrinking of memory structures. It then behooves AMD to dislodge their cache from their logic, for future processors. (same obviously why they did the same with GPU's starting with the 7000-series, but without 3D-stacking)
It means "the stacking, the"
Finally! The society for putting things on top of other things!
this video is far breader most
"aforementioned" ...
If we are to keep 3D stacking, the chips will need to start having internal capillary cooling systems to pull heat away from the chips and onto its packaging to prevent serious thermal throttling.
Stacking two dies will never pass for an adult...
>iPhone 5S, first introduced a decade ago in 2013
i'm still using mine, ouch
Die hard: Stacking
This channel has been en fuego so far this year. These videos are a clear as, and as efficient as, the video classes on semiconductor technology and processes at Motorola University. However, because they cover developments and feature images from a wide variety of vendors and sources, they are far more catholic in their breadth of knowledge. Terrific work!
...Far more *catholic*??
@@werdfeefs7027, as in comprehensive, universal: broad in sympathies, tastes, or interests.
That ".5 more 'D'" might be neat, but, maybe I should listen to the presentation again to try to better comprehend what is "D" and what is the other 2.5 of it.
D means "dimension"
2D is flat surface
3D means volume
2.5D here are chips where parts (compute/cache) aren't on top of each other, but there's a layer of vertical+horizontal wires below
The channel is too focused on CPU/GPU.
Image sensors were the driver for 3D stacking. Direct wafer bonding (with Cu to Cu direct connects) of the pixel sensor chip to the image sensor processor is in high volume mass production since years. Everybody has such product today. The technology is amazing the pixel sensor wafer is in the end only 10um thick and processed from both side with just tens nm overlay shift. Also the wafer to wafer overlay shift much less than 1um.
Todays smartphone cameras rely on that technology. You have very small pixels for small/cheap chips with many pixels but still low noise.
I'm disappointed you didn't reference the "society for putting things on top of one another"
This is so cool! I can't wait for Neural Net Processors!
The linear algebra tensor neural net like in the New riscV compounds or the real NN with associatons and long signal propagation?
Since chips are technically still "rocks" we are still in the stone age. Once we get out of the oort cloud we may see a new age begin.
I rather die a chiplet than die stacking