Not Just Chips: The Challenges of Scaling Beyond Moore’s Law and Into the World of 3DHI

The Challenges of Scaling Beyond Moore’s Law and Into the World of 3DHI
John Park
Cadence
While Moore’s Law still provides huge performance, power, and area (PPA) advantages to some, most semiconductor companies no longer see it as the best technological and economic path forward for their next-generation designs. There are several trends that have contributed to the slowing/ending of Moore’s Law including the physical size limitations of a single monolithic die (reticle limit), low yield tied to large die sizes, and to many, the overall cost of designing at the most advanced
nodes (hundreds of millions of dollars). Instead, the future holds 3D heterogeneous architectures-the world of More-than-Moore and a new wave of expansion to embrace multi-chiplet 3D packaging to accommodate the changing landscape of microelectronics. However, moving to 3D heterogeneous integration (3DHI) comes with many challenges. These
challenges span the 3DHI ecosystem and have a huge impact on the EDA tools/flows required to develop state-of-the-art 3DHI designs. This presentation will talk about the industry trends and outline many of
the design challenges when engineering teams pivot from monolithic die to 3DHI.