Thanks very much for this channel and prof. Hajimiri! There are many video about Analog circuit, but I think Prof. Hajimiri gives the best. Many others are just focus on the different structure and it's pros or cons. I think the most beautiful and funny thing in analog design is the trade-off. You always have to play with those trade-offs, and Prof. Hajimiri gives some very interesting trade-offs and I have learned a lot about that!
00:02 Op amps are building blocks with differential input and single-ended output. 02:24 Current mirror ratio determines gain and output resistance. 07:04 Op-amp input range is limited by supply voltage. 09:25 Operational amplifier design considerations for high and low voltages. 14:41 Common mode behavior of MOS transistors 16:48 Differences in gain for MOs devices 21:23 Adjusting the current for the differential pair 23:33 Choosing a moving voltage over a fixed voltage for common mode 27:51 Using a floating mirror to adjust threshold voltage. 30:25 Creating a reference branch to control current 34:56 Design considerations for operational amplifier properties 37:01 Op-Amp design involves trade-offs in transistor sizing and channel length. 40:53 Minimum channel length and its impact on device performance. 43:29 The importance of choosing the right W/L ratio for MOS Op-Amp design. 47:49 The video discusses various design examples of MOS Op-Amp 50:30 The input ranges for the op-amp design examples are being discussed. 54:40 Kassel folded cascode offers more gain due to current distribution 56:56 Telescopic cascode amplifiers can achieve high gains and differential outputs. 1:02:43 Cascode design has a voltage level problem. 1:04:54 Adding a follower to adjust voltages and the problem with supply voltage changes. 1:09:13 Invert the whole thing to create a more complete object 1:11:34 Design considerations for op-amp output stages Crafted by Merlin AI.
Love your videos but I'm pretty sure your analysis of the 5-transistor-OTA VICM max is incorrect. You comment that the input can go above VDD but that is not the case due to the diode-connected transistor (which you did not mention) on the left. The diode-connected transistor sets the drain voltage to VDD - Vgs = VDD - Vov - Vtp. The input can go one threshold above that: Vicm,max = VDD - Vov - Vtp + Vtn ~ Vdd - Vov (assuming Vtp ~ Vtn).
no. The drain voltage (drain potential to be more correct) of the left transistor is different from the drain voltage of the right transistor. The professor analysis is correct t
fjord2141 is correct. The left side input NMOS transistor will get squeezed because of diode drop (VT+del_Vp) from PMOS current source. Its gm will drop resulting in lower overall gain. Hence ViCM (max) is ~ VDD-delVp assuming mag(VTp) = mag(VTn)
I think you are right. The input common-mode maximum voltage should also take into account the left-branch diode-connected PMOS and the left NMOS pair. The Vcm,max should be one overdrive voltage below VDD. What the professor analyzed is roughly one overdrive voltage above VDD.
Hi Professor, Can I please ask a question @10:02 Your equation suggests the drain of PMOS M3 can be as high as Vdd-delta(Vgs). I would agree with you if we were analyzing the differential mode. But you also discussed the common mode input condition. Then the drain of both PMOS should be the same voltage and the max drain voltage of PMOS has to be less than Vdd - Vsg_3 instead of Vdd-delta(Vgs) due to the left diode connected PMOS Thank you a lot if you can correct me if I am wrong!
Dear professor, at minute 13:49 you solved me a doubt that have remained in my brain from the introduction of ΔVgs. You used often that voltage (ΔVgs ) as it was fixed, however by definition it is ΔVgs = Vgs - VT, so to determine if the mosfet is working in the triode region, It has to be Vgs>VT and Vds
The PMOS current sources coming off the Vt/R IREF generator might as well be cascoded also, this would be better. Do you have any job openings for analog designers ? :)
25:32 prntscr.com/n9saq0 - Professor could you please see this. We put T3 there to provide minimal T12 and T22 gate voltage such that there is JUST enough room for Vt and their overdrive voltage (the voltage necessary to provide half of the common reference current), plus one more overdrive voltage of T11 and T21 that will also enable drains of T12 or T22 to have the lowest possible voltage (Vt bellow Gate voltage of T12 and T22)? Because Ifer2 is not the same as Iref1 and overdrive of T3 must be two times overdrive of T11 or T12 (as it is across both of them) we can size the T3 in such a way that with its smaller bias current provides larger Vgs? Thank you immensely professor, you have changed my carrier probably!
Thanks very much for this channel and prof. Hajimiri! There are many video about Analog circuit, but I think Prof. Hajimiri gives the best. Many others are just focus on the different structure and it's pros or cons. I think the most beautiful and funny thing in analog design is the trade-off. You always have to play with those trade-offs, and Prof. Hajimiri gives some very interesting trade-offs and I have learned a lot about that!
00:02 Op amps are building blocks with differential input and single-ended output.
02:24 Current mirror ratio determines gain and output resistance.
07:04 Op-amp input range is limited by supply voltage.
09:25 Operational amplifier design considerations for high and low voltages.
14:41 Common mode behavior of MOS transistors
16:48 Differences in gain for MOs devices
21:23 Adjusting the current for the differential pair
23:33 Choosing a moving voltage over a fixed voltage for common mode
27:51 Using a floating mirror to adjust threshold voltage.
30:25 Creating a reference branch to control current
34:56 Design considerations for operational amplifier properties
37:01 Op-Amp design involves trade-offs in transistor sizing and channel length.
40:53 Minimum channel length and its impact on device performance.
43:29 The importance of choosing the right W/L ratio for MOS Op-Amp design.
47:49 The video discusses various design examples of MOS Op-Amp
50:30 The input ranges for the op-amp design examples are being discussed.
54:40 Kassel folded cascode offers more gain due to current distribution
56:56 Telescopic cascode amplifiers can achieve high gains and differential outputs.
1:02:43 Cascode design has a voltage level problem.
1:04:54 Adding a follower to adjust voltages and the problem with supply voltage changes.
1:09:13 Invert the whole thing to create a more complete object
1:11:34 Design considerations for op-amp output stages
Crafted by Merlin AI.
Amazing. For IC designer nothing can be better than this.
@1:09:00 Good information: from stability perspective, it's good to have more gain on the 2nd stage of op-amp.
think about architectural changes not the parametric change in circuit design..very important point
10:29 No. You are forgetting the other branch of the diff pair. The diode connected PMOS will crunch the NMOS in the diff pair earlier.
Love your videos but I'm pretty sure your analysis of the 5-transistor-OTA VICM max is incorrect. You comment that the input can go above VDD but that is not the case due to the diode-connected transistor (which you did not mention) on the left. The diode-connected transistor sets the drain voltage to VDD - Vgs = VDD - Vov - Vtp. The input can go one threshold above that: Vicm,max = VDD - Vov - Vtp + Vtn ~ Vdd - Vov (assuming Vtp ~ Vtn).
True
Yeah, wondered about the same thing. His analysis would be true for a diff pair with differential output
no. The drain voltage (drain potential to be more correct) of the left transistor is different from the drain voltage of the right transistor. The professor analysis is correct t
fjord2141 is correct. The left side input NMOS transistor will get squeezed because of diode drop (VT+del_Vp) from PMOS current source. Its gm will drop resulting in lower overall gain. Hence ViCM (max) is ~ VDD-delVp assuming mag(VTp) = mag(VTn)
I think you are right. The input common-mode maximum voltage should also take into account the left-branch diode-connected PMOS and the left NMOS pair. The Vcm,max should be one overdrive voltage below VDD. What the professor analyzed is roughly one overdrive voltage above VDD.
Great lecture! Thanks so much for posting these!
Hi Professor, Can I please ask a question @10:02
Your equation suggests the drain of PMOS M3 can be as high as Vdd-delta(Vgs). I would agree with you if we were analyzing the differential mode.
But you also discussed the common mode input condition. Then the drain of both PMOS should be the same voltage and the max drain voltage of PMOS has to be less than Vdd - Vsg_3 instead of Vdd-delta(Vgs) due to the left diode connected PMOS
Thank you a lot if you can correct me if I am wrong!
Dear professor, at minute 13:49 you solved me a doubt that have remained in my brain from the introduction of ΔVgs. You used often that voltage (ΔVgs ) as it was fixed, however by definition it is ΔVgs = Vgs - VT, so to determine if the mosfet is working in the triode region, It has to be Vgs>VT and Vds
the best!
That is great ,thanks for sharing professor ❤
Thank you Sir, for this great lecture.
The PMOS current sources coming off the Vt/R IREF generator might as well be cascoded also, this would be better. Do you have any job openings for analog designers ? :)
Shouldn't floating current mirror in the band-gap reference be connected differently, like in this picture prntscr.com/n9tdgk?
At 1:00:00, the bias voltage at the gates of folded cascodes as well as that of active loads arent discussed. Can anyone comment on that?
25:32 prntscr.com/n9saq0 - Professor could you please see this. We put T3 there to provide minimal T12 and T22 gate voltage such that there is JUST enough room for Vt and their overdrive voltage (the voltage necessary to provide half of the common reference current), plus one more overdrive voltage of T11 and T21 that will also enable drains of T12 or T22 to have the lowest possible voltage (Vt bellow Gate voltage of T12 and T22)? Because Ifer2 is not the same as Iref1 and overdrive of T3 must be two times overdrive of T11 or T12 (as it is across both of them) we can size the T3 in such a way that with its smaller bias current provides larger Vgs? Thank you immensely professor, you have changed my carrier probably!