You are correct. Assuming the that output of the current source driving the base can be as low as a -Vcc+Vsat, the the output can go as low as -Vcc+Vsat+Vbe. Thank you for noticing this. I pinned your comment so others can see it and make the correction.
This is the 3rd time i am following this Lecture. I have set the speed to 0.75 to make sure to understand every explanation. I am starting to understand it...Thank you Professor Ali.
@45:50: Regarding Vbias, it can be approximated as the sum of Vce,sat (tail current source) and Vce,sat (differential input), plus Vbe (cascode npn), which totals to 0.3V + 0.3V + 0.7V = 1.3V. However, the three diode-connected branches sum up to about 2.1V (3 * 0.7V = 2.1V) above ground. Therefore, there exists a discrepancy. Wouldn't it be preferable to utilize only two diode-connected branches, which would bring it closer to Vbias by 1.4V?
Could have we biased the two cascoded transistors ontop of differential input transistors as in previous lecture, that is with two NPN transistors from their base to the common current source transistor?
I think you are referring to the MOS example. In my view, that's possible but cascode bias here isnt that important due to low swing at the output of differential stage.
45:57 Sir, why did you choose exactly 3 Vbe's above ground, Vbias can be somewhat more or less than that. Does this way of biasing allow that flexible range and get the correct biasing? Many thanks for the lecture. I remember looking at the datasheet(before watching your lectures) of an old opamp(maybe IC741 or something) and it's schematic completely filling the page with transistors connected in all fashions. Unable to determine which transistor is doing what, I quickly skipped the schematic part, else the confusion would have toasted my brain.
I am wondering the same. Based on reflection rule, the impedance seen in emitter is beta divided by the impedance at the base. So that diode-connected npn emitter resistance should be back to 50 Ohm.
Isn't there an issue with the PNP second stage transistor which gets placed around 15:10? Together with preceding PNP emitter-follower it connects Vcc+ over 2 diode drops directly to ground. this will result in a nice attenuator producing heat and smoke.
No, that is not correct.There is no direct path to ground from Vcc. There is always a base-collector junction in the path to -Vcc, which will be reverse biased under normal operations. Note the current sources that will be replaces by transistors later.
@@AliHajimiriChannel I see my reasoning is wrong. What still puzzles is me that in my (probably not accurate) simulation the preceding PNP connects the base of the gain stage (PNP placed at 15:10) with its emitter through its collector to ground. once that PNP gets turned on it provides a low impedance connection from Vcc to ground.
At 40:14 for pnp to go as low as -vcc+vsat wouldn't require it's base go -vcc+vsat-vbe, that is bellow -vcc?
You are correct. Assuming the that output of the current source driving the base can be as low as a -Vcc+Vsat, the the output can go as low as -Vcc+Vsat+Vbe. Thank you for noticing this. I pinned your comment so others can see it and make the correction.
This is the 3rd time i am following this Lecture. I have set the speed to 0.75 to make sure to understand every explanation. I am starting to understand it...Thank you Professor Ali.
Great to see the knowledge accumulatively combining to a decent op-amp!
Pretty great, I’m a recent BS EE grad about to start a MS. program, finding these videos a great refresher
@47:00: The BTJ two-stage amplifier appears to be notably more complex when compared to the CMOS two-stage amplifier.
@45:50: Regarding Vbias, it can be approximated as the sum of Vce,sat (tail current source) and Vce,sat (differential input), plus Vbe (cascode npn), which totals to 0.3V + 0.3V + 0.7V = 1.3V. However, the three diode-connected branches sum up to about 2.1V (3 * 0.7V = 2.1V) above ground. Therefore, there exists a discrepancy. Wouldn't it be preferable to utilize only two diode-connected branches, which would bring it closer to Vbias by 1.4V?
Excellent !
What would set the nominal output voltage at 0 volts? I think it'd be set by the input common-mode voltage. Thats something that hasnt been discussed.
Could have we biased the two cascoded transistors ontop of differential input transistors as in previous lecture, that is with two NPN transistors from their base to the common current source transistor?
I think you are referring to the MOS example. In my view, that's possible but cascode bias here isnt that important due to low swing at the output of differential stage.
MOS example was a single stage design so the output of gain stage could easily start clipping if cascodes arent properly biased.
45:57 Sir, why did you choose exactly 3 Vbe's above ground, Vbias can be somewhat more or less than that. Does this way of biasing allow that flexible range and get the correct biasing?
Many thanks for the lecture.
I remember looking at the datasheet(before watching your lectures) of an old opamp(maybe IC741 or something) and it's schematic completely filling the page with transistors connected in all fashions. Unable to determine which transistor is doing what, I quickly skipped the schematic part, else the confusion would have toasted my brain.
1) current source VCE
2) Input pair VCE
3) Cascode VCE
i.e. 3 Vbes needed.
At 36:24 for impedance 5koms, wouldn't it requires to be divided by beta based on the reflection rule?
I am wondering the same. Based on reflection rule, the impedance seen in emitter is beta divided by the impedance at the base. So that diode-connected npn emitter resistance should be back to 50 Ohm.
Isn't there an issue with the PNP second stage transistor which gets placed around 15:10? Together with preceding PNP emitter-follower it connects Vcc+ over 2 diode drops directly to ground. this will result in a nice attenuator producing heat and smoke.
No, that is not correct.There is no direct path to ground from Vcc. There is always a base-collector junction in the path to -Vcc, which will be reverse biased under normal operations. Note the current sources that will be replaces by transistors later.
@@AliHajimiriChannel I see my reasoning is wrong. What still puzzles is me that in my (probably not accurate) simulation the preceding PNP connects the base of the gain stage (PNP placed at 15:10) with its emitter through its collector to ground. once that PNP gets turned on it provides a low impedance connection from Vcc to ground.
🙏
Thats genius