Latches and Flip-Flops 3 - The Gated D Latch
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- Опубліковано 4 жов 2024
- This is the third in a series of videos about latches and flip-flops. These bi-stable combinations of logic gates form the basis of computer memory, counters, shift registers, and more. In particular, this video covers the gated D latch, otherwise known as the data latch or simply the D latch. It begins by reviewing the gated SR latch, including the risk of making both inputs high at the same time which results in a race condition and therefore an unpredictable state. It then shows how this problem can be overcome by a gated D latch. Two ways of building a gated D latch are covered and its behaviour is illustrated with a timing diagram. The videos that follow this one build upon the principles covered here and include the clocked D latch, edge triggered pulse latches and the master slave D type flip flop.
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Thank you so much! Finally understand timing diagrams because of this video
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Thank you, The video was very patient and concise in explaining the concepts and was very useful
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best video to explain D latch
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I finally understand gated d latches. Thank you!
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You're welcome. Naughty students might disagree with you. :)KD
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@@ComputerScienceLessons it's a shame i wasn't able to find a JK flip-flop video on your channel. Don't get why is supposed to be acting as a toggle at 1 1. The funny thing is that my teacher wasn't able to explain it to me :D
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I really liked the first two videos, but this one is very confusing. One thing I don't understand is why this circuit is called a latch when it does not latch actually. The difference in its behavior is clear when compared to the previous video (#2). This circuit does not work with pulses (see 2:28). It requires that the D input is already latched/sustained in order to operate like the latch it is supposed to replace (gated SR latch). The output Q is latched only as long as the Set button (D input) is sustained. Up to this point, Q acts as a buffer for D without any latching properties. It doesn't only fix a problem of gated SR latch, it also changes its operation. Another problem I see in this explanation is the behavior of the E input which is a little bit different here. In the previous video, the role of the E input was only to enable or disable the functionality of the set and reset buttons/signal. In this circuit the E input has also another function. It can affect/change the output (see 4:19 , 5:58 and 6:13).
Anyone care to clear up my confusion?
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Love you too. :)KD
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Can you show the Boolean expressions and talk a little bit about them
I'll take a look at it :)KD
Looks like the lines between the NAND gates should be red at t=91s. Am I wrong?
That unpredictability could be useful in ways can it? That has the potential to be an A randomizer of sorts.
Have you written any books on the subjects? Computers?
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2:29 Hey, shouldn't this only be an and gate, not a nand gate please? For the inputs, not the SR latch part
what.. before you said the nand gated SR latch is active low.. because both S & R are always high..
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I don't understand why when we have D=0 and En=0 we continue getting Q=0 . If I am correct , after the 1st upper NAND we get 1 and after the first down NAND we get 1 . How can we determine then that Q=0 ??? It isn't obvious from the logic diagram of NAND...Anyone help please ??
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If we ever meet, mine's a cheeseburger :)KD
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can d latch only be with nand gates?
What about the jk flip flop
Should have a video on this in a couple of weeks - I hope. Rather busy with the day job at the moment I'm afraid :)KD
@@ComputerScienceLessons were can i learn for Multiplexer and decoders
Hi David. If you watch my playlist on DRAM, you will see that decoders and multiplexers are covered to some extent in parts 3 and 4. :)KD
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Molto interessante, ma le tecnologie in inglese non è facile capirle
Mi dispiace ma il mio italiano non è buono. Forse puoi tradurre le didascalie.