In my 12 years of engineering education, you are first professor who clearly and concisely explained the SR latch operation without causing any confusion. You are a genius. Thank you sooo much
@@ComputerScienceLessons The changing of colours like we are watching a super slow speed playback reallly really helps to understand what is happening, thanks!
1:30 NOR gate and NAND gate explained 2:25 NOR gate and NAND gate can be used to make an S-R latch 2:35 Cross-coupling of 2 NOR gates in an S-R latch 3:17 Starting state of this S-R latch example 3:55 Resetting the latch 4:17 Pulse removed 4:25 Applying another pulse and implications 5:05 Implications of applying a pulse to S 5:27 Truth table 6:15 Truth table after applying a set pulse 6:25 Truth table after removing the set pulse 7:15 Race condition 8:00 Active High S-R Latch Explained 8:41 Truth table for Active High S-R Latch 9:20 Active Low S-R Latch (i.e. built from NAND gates) 9:44 Forbidden state of the S-R latch built from NAND gates 10:00 Summary 10:37 Switch bounce problem 11:37 Examples of applications of an S-R latch
You mean that our hearing is racist or our ability to understand certain accents is racist? I guess it's very racist that we haven't started making every language and culture an obligatory subject in school yet, huh? We can afford the extra decade. I hope you better understand all Scottish and Irish accents perfectly, otherwise you're a total biggot. And God help you if there's any African accent you don't understand flawlessly!
Indian english in general is different to british english. i dont speak english as a first language, and british english was the english i had to study, so from a non english speaking background a subset of english i learnt is easier to understand than one with a different set of english. that being said some indian youtubers are very helpful
Thank you! Thank you for you hard work, as a scientist and an educator! Thank you for putting the time into these videos! Thank you being British, as sometimes I forget I'm not watching a great BBC documentary! Thank you, Sensei! Thank you!
I am currently taking a digital fundamentals class for my computer degree and I have been struggling a lot with these chapters that are starting to cover latches and flip flops. I have a difficult time comprehending material simplify by reading out of the text book, and I've tried several videos on UA-cam to help. None of them have worked; they have still been too confusing. Your channel has been a blessing so far. Very easy to understand on how slow you explain the information and the visuals are good. I'm going to continue watching them all and taking notes. Thank you!
That’s great to hear, shows you have not given up and you are trying to understand, learn by finding different ways. Small tip: You mentioned you had trouble understanding the concept by reading the prescribed text book right, now that you know this topic, go back and read the chapters covering this in the book. This time concentrate on how the author is trying to communicate this information in the book. Why his language constructs are difficult to understand, how you can break it out so that next time you can learn a difficult concept by reading a book written in a convoluted language.
@Sundeep Kumar That's also my question... because in the very, very beginning there is no signal from anywhere, so do we regard that all as 0s everywhere? Then we get two 1s after both NOR gates which feed back to each other and their input becomes 0 and 1 for both, which then means their output is two 0s, which means makes their inputs once again all 0s, which makes their outputs two 1s again, etc, etc. Endless loop. Is a flip-flop in such an endless loop eithout any electricity and any input? I really need someone to define the beginning for me, how does it all start. If it starts with the S signal setting it, then all those 0s are valid input, so why aren't they valid before the S signal sets it? That's really confusing to me.
@@yuurishibuya4797 That's a good tip! Another tip I would give is to try qnd imagine visually what the author is trying to say with words and try drawing it, maybe even draw it in panels just like the panels of a video explaining it.
I am offering my college degree i got confused today in my computer architecture lecture.With this video i am now a good "comprehender"! wishe that i get a lot of your tutorials to enhances most troubling concepts. you are a great teacher. Thank you.
I'm a distance-learning student going to Arizona State (electrical engineering) and I cannot thank you enough for these videos. It's difficult to get help from the professor as he teaches in the classroom, and the forum we use, Piazza, isn't always an active forum where people get a hold of you quickly. At least I can rely on somebody else's different point of view on this stuff. Thank you very much!
This is the first video I've come across that explains how these latches actually work and doesn't just input the values of the truth table onto a graphic. Thank you! It finally makes sense.
This is why 11 Lakh views are present for this video but it is not showing on the top.. The last 11.48 Minutes is excellent and I really understood this mysterious SR thing.
you are a life saver, now I understand the concept. Other youtube channesls were going through a lot of what you said like we already knew. This is easy to understand for any beginnger
Dude. This is explained so clearly. The graphics really help a lot too! Exactly what I needed... I'm watching the whole series tonight. Thank you for the time you put into this!!
My department head teaches Digital Logic Fundamentals and bless her heart she has tons of experience in the industry and has 2 PHDs. She's super nice and extremely helpful but she can't explain a concept concisely to save her life. This is an easy concept that was just presented very poorly to me. Thanks!
You are an amazing instructor. I've searching all over youtube and the videos that I've watched are not as clear and coherent as this video. My instructor has explained this concept but as it today after a couple of weeks taking his class, I was completely lost by his inefficient way to teach this "complicated" subject, but as it right now, I finally understand flip-flops and latches but I'm afraid that is too late and I may end up withdrawing from the class that I'm currently taking. One last thing, you are blessed with the gift of teaching. Thank you so much and god bless you.
Thanks for your very kind comments Aaron. I must admit, I had to do a lot of digging around to get this subject clear in my own mind. The text books I read had a lot of errors in them but I got some fantastic support on the electrical engineering Stack Exchange website. electronics.stackexchange.com/. Ben Eater is brilliant too ua-cam.com/users/eaterbc. It would be a shame to give up a subject that you might have loved because of one instructor - I hope you make the right decision and that things work out well for you - and good luck.
Thanks, this was very useful. I appreciate your explanation of the outputs being denoted as inverse and the explanation of the invalid state. This part gets glossed over in many other people's explanations (probably because they don't have a very deep understanding of the thing they are attempting to explain). Thanks again
Great video! I have already learned the function of SR latch, but I was confused by different realizations of the circuit which are perfectly explained here.
Thank you so much, your video helps a lot. My textbook didn't explain the nor gate and the nand gate well like you did and I came across to your video that I am start learning the flip lops and latches. This video is very great!
You've got a subscriber mate, You are wayyyy better than my teacher, and your explanation directly goes to the permanent area of brain. Great Job, well done, God Bless You!!!!! Keep up the good work!
Did you make a mistake 8:52 when you said that the SR input are held high? Because isn't the NAND logic latch are active low like you said at 10:22 later?
At 3 minutes and 21 seconds into this video how exactly does someone know that the top output is a 1? When what you need to know is that the top input of the set inputs OR gate is a one when bottom input of the reset OR gate needs to be know first to know that.
In real life, it's startup state is considdered random. Because any of the two states is determined by wich nor gate is stronger than the other to force a 1 on the output. It's why whenever a cpu starts up all registers need to be reset and put in a known state for it to function propperly. In the video he assumes the top one is set because it helps make the explination simpler.
I have a similar question. How do you know that both of the inputs for the top gate are 0 when the second input of the top gate is dependent on the output of the bottom gate, which is in turn dependent on the output of the top gate? It seems paradoxical. Clearly I'm missing some unspoken rule on the ordering or just misunderstanding something?
The starting state is determined at the moment the power suplied. its random Q can be either 1 or 0. but once its determined the the other become imedeately the opposite of that .
Explained in a nice easy to understand way really well, thanks very much! Wish I just watched this video first instead of wasting hours of reading my textbook
Very well done lesson. One of the sources of confusion is that the two gates are drawn in parallel. This is elegant but makes it harder to work out the series of events. Just redraw the circuits as two gates in series and it becomes easier to see the positive feedback path and then to visualise the timelines.
at 3:28, why is the top nor already producing an output but the bottom one isn't? the setup is symetric, so both should be on instantly, then switch each other off and on again in an endless loop.
Propagation delays which depend on external conditions mean that it is highly unlikely both inputs will be set to low at the same time (and it's low voltage that represents 0, not no voltage). Nevertheless, the circuit will reach equilibrium as soon as a pulse is applied to just one of the inputs. :)KD
Thank you so much for this easy to follow explanation! My professor has zero interest in actually teaching lessons in class and just tells us to read the text book. I might actually pass this class now😅
Those who are confused, Q= House of 1 & Q°= House of 0. Therefore, if Q has a value of "1", the Latch stores 1. It's because Q is the House of 1. And, if Q° has a value of "1", the Latch stores 0. It's because Q° is the House of 0.
One doubt at 3:27 ... initially how can u consider Q is high? bc for the top NOR gate, one input is R=0 and other one is not defined right? it is the output of bottom NOR gate who's one input is output of top NOR gate.. damn i feel like inception
For active low latch, do the S and R normally have a pulse and then to make a change you remove a pulse? Or do they not normally have a pulse and you provide a low pulse to make a change?
Why do you assume the outputs for Q and Q complement at 3:16? Who's to say that Q has to be high? I don't understand why it's just assumed to be that way.
With NOR SR latch, I don't understand how the gates can output a signal initially. You need two input signals for the NOR gate but initially there is only one input for each of the NOR gate (R and S) since the Q and NOT Q outputs are not generated yet. Can NOR gates output a signal given only one input signal?
Really commendable job!!! Keep Rocking!!! Saw this video, and immediately subscribed!! I like the way you approached the topic. Great for beginners. Thanks a ton for this!!!
Well, I have always considered the latches as some sort of electronic toggle switches. If the leaver is up the input is one, when the leaver is down, the input is the opposite. So it's like the electronic equivalent of a mechanical toggle switch
the thing is: the output differs depending on whether we start by outputing S, then transferring its output to an input of the NOR gate with R or outputing R then transferring the output as an input with S. Like for the first SR Latch made of NOR gates, assuming S=0 and R=0 If we start with S=0, Q'=S=0 then (R+Q')'=(0+0)'=1 so Q=1 BUT if we start with R, it flips: R=0, Q=R=0 then (S+Q)' = (0+0)'=1 so Q'=1. Completely different answers. So, which is the dominant path here?
You're absolutely right. This used to bother me because I overthink things. The way i see it, the answer is: race condition. Basically, both results are valid, as seen in the truth tables at 10:01 . You don't care whether Q or Q' is set. All you care about is the fact that they are opposite. After all, this is a Set Reset latch, so you can put it into a favorable default state if it initializes into an undesirable state. As long as R and S do not violate the one illegal condition for whichever latch, you will have a latch that initializes into one of two states, which can be adjusted by the inputs as needed. To answer your question explicitly, there is no dominant path. It all depends on the propagation delay of the components.
@@mikey.audio. I overthink too. Thank you for your simple but effective answer. It clears my doubts and persuades me to deal with the question later when I learn more about the delay.
In my 12 years of engineering education, you are first professor who clearly and concisely explained the SR latch operation without causing any confusion. You are a genius. Thank you sooo much
You flatter me. Thank you. :)KD
@@ComputerScienceLessons The changing of colours like we are watching a super slow speed playback reallly really helps to understand what is happening, thanks!
12 years of engineering education and you're still learning about SR latch. Oof much?
Or a failure of education.
@@lumerify He never said that. Read the comment again.
This video better than any other explanation, short to the point
Are you kidding? 12 minutes for something that can be explained in 3
Marquis Chan nice
@@supermariozaken 3 minutes? if anything he covered the topic quite efficiently but it was only long due to him slowly speaking for his viewers.
@@supermariozaken where's your 3 minute explanation? Please share a link
the game lumber tycoon 2 has these stuff (roblox)
1:30 NOR gate and NAND gate explained
2:25 NOR gate and NAND gate can be used to make an S-R latch
2:35 Cross-coupling of 2 NOR gates in an S-R latch
3:17 Starting state of this S-R latch example
3:55 Resetting the latch
4:17 Pulse removed
4:25 Applying another pulse and implications
5:05 Implications of applying a pulse to S
5:27 Truth table
6:15 Truth table after applying a set pulse
6:25 Truth table after removing the set pulse
7:15 Race condition
8:00 Active High S-R Latch Explained
8:41 Truth table for Active High S-R Latch
9:20 Active Low S-R Latch (i.e. built from NAND gates)
9:44 Forbidden state of the S-R latch built from NAND gates
10:00 Summary
10:37 Switch bounce problem
11:37 Examples of applications of an S-R latch
Finally a perfect explanation with a great and easy to understand accent
Thanks god it's not in indian accent lol or I would fail man!
that's racist
No, it's not racist, as he is just saying that the indian accent is very hard to understand, and I agree.
You mean that our hearing is racist or our ability to understand certain accents is racist? I guess it's very racist that we haven't started making every language and culture an obligatory subject in school yet, huh? We can afford the extra decade. I hope you better understand all Scottish and Irish accents perfectly, otherwise you're a total biggot. And God help you if there's any African accent you don't understand flawlessly!
Indian english in general is different to british english. i dont speak english as a first language, and british english was the english i had to study, so from a non english speaking background a subset of english i learnt is easier to understand than one with a different set of english.
that being said some indian youtubers are very helpful
Thank you!
Thank you for you hard work, as a scientist and an educator!
Thank you for putting the time into these videos!
Thank you being British, as sometimes I forget I'm not watching a great BBC documentary!
Thank you, Sensei!
Thank you!
You are very welcome and you are very kind. Thank YOU :)KD
I am currently taking a digital fundamentals class for my computer degree and I have been struggling a lot with these chapters that are starting to cover latches and flip flops. I have a difficult time comprehending material simplify by reading out of the text book, and I've tried several videos on UA-cam to help. None of them have worked; they have still been too confusing. Your channel has been a blessing so far. Very easy to understand on how slow you explain the information and the visuals are good. I'm going to continue watching them all and taking notes. Thank you!
That's great to hear. Thanks for the lovely feedback.
That’s great to hear, shows you have not given up and you are trying to understand, learn by finding different ways.
Small tip: You mentioned you had trouble understanding the concept by reading the prescribed text book right, now that you know this topic, go back and read the chapters covering this in the book. This time concentrate on how the author is trying to communicate this information in the book. Why his language constructs are difficult to understand, how you can break it out so that next time you can learn a difficult concept by reading a book written in a convoluted language.
@Sundeep Kumar That's also my question... because in the very, very beginning there is no signal from anywhere, so do we regard that all as 0s everywhere? Then we get two 1s after both NOR gates which feed back to each other and their input becomes 0 and 1 for both, which then means their output is two 0s, which means makes their inputs once again all 0s, which makes their outputs two 1s again, etc, etc. Endless loop. Is a flip-flop in such an endless loop eithout any electricity and any input? I really need someone to define the beginning for me, how does it all start. If it starts with the S signal setting it, then all those 0s are valid input, so why aren't they valid before the S signal sets it? That's really confusing to me.
@@yuurishibuya4797 That's a good tip! Another tip I would give is to try qnd imagine visually what the author is trying to say with words and try drawing it, maybe even draw it in panels just like the panels of a video explaining it.
Your teaching style is incredible. Thank you for all the work of sharing these lessons for free!
Thank you, and you are most welcome :)KD
BY FAR the best SR Latch and FlipFlop explanation video series on UA-cam! Please keep making videos. Excellent
That's lovely to hear. Thanks a million.
Finally excellent source for Logic Circuit, Thanks from Turkey.
You are most welcome :)KD
I am offering my college degree i got confused today in my computer architecture lecture.With this video i am now a good "comprehender"! wishe that i get a lot of your tutorials to enhances most troubling concepts. you are a great teacher. Thank you.
One the clearest most concise videos out there on SR Latches. Much appreciated !
The question is who's running first the upper nor gate? or the lower nor gate from the previous state in order to go to the next state of q and q not?
great explanation and I appreciate that a practical example was also included in the video which made it really easy to understand :)
Thanks for saying so - I appreciate the feedback
My textbook tried to do this in two pages of text with no words. Thank you for making this bearable.
I'm a distance-learning student going to Arizona State (electrical engineering) and I cannot thank you enough for these videos. It's difficult to get help from the professor as he teaches in the classroom, and the forum we use, Piazza, isn't always an active forum where people get a hold of you quickly. At least I can rely on somebody else's different point of view on this stuff. Thank you very much!
ASU Industrial Engineering student here i have to take digital design fundamentals. This is a better explanation than my professor.
I didn't understand SR latches at all until I saw this. Thank you so much!
This is the first video I've come across that explains how these latches actually work and doesn't just input the values of the truth table onto a graphic. Thank you! It finally makes sense.
This is why 11 Lakh views are present for this video but it is not showing on the top.. The last 11.48 Minutes is excellent and I really understood this mysterious SR thing.
This is one of the best explanations of the SR latch that I have ever seen.
Kind of you to say so. Thanks :)KD
you are a life saver, now I understand the concept. Other youtube channesls were going through a lot of what you said like we already knew. This is easy to understand for any beginnger
Delighted to help :)KD
Dude. This is explained so clearly. The graphics really help a lot too! Exactly what I needed... I'm watching the whole series tonight. Thank you for the time you put into this!!
Thank you - I really appreciate your comment
Try not to overdose on it. Little and often is best.
Great video thanks! Best part is that you switch the inputs in realtime.
Thanks a million
best video on electronics ive come across so far
Thank you :)KD
I felt very sophisticated watching this tutorial
:)KD
My department head teaches Digital Logic Fundamentals and bless her heart she has tons of experience in the industry and has 2 PHDs. She's super nice and extremely helpful but she can't explain a concept concisely to save her life. This is an easy concept that was just presented very poorly to me. Thanks!
This video is clear and concise. Well done, sir.
Thank you :)KD
You are an amazing instructor. I've searching all over youtube and the videos that I've watched are not as clear and coherent as this video. My instructor has explained this concept but as it today after a couple of weeks taking his class, I was completely lost by his inefficient way to teach this "complicated" subject, but as it right now, I finally understand flip-flops and latches but I'm afraid that is too late and I may end up withdrawing from the class that I'm currently taking. One last thing, you are blessed with the gift of teaching.
Thank you so much and god bless you.
Thanks for your very kind comments Aaron. I must admit, I had to do a lot of digging around to get this subject clear in my own mind. The text books I read had a lot of errors in them but I got some fantastic support on the electrical engineering Stack Exchange website. electronics.stackexchange.com/. Ben Eater is brilliant too ua-cam.com/users/eaterbc. It would be a shame to give up a subject that you might have loved because of one instructor - I hope you make the right decision and that things work out well for you - and good luck.
You explain better than university professors. Thank you!
You are most welcome. Thanks for commenting :)KD
Clear and concise, it shows just how well you know your stuff. Thank you so much
You are very kind. Thank you :)KD
Thanks, this was very useful. I appreciate your explanation of the outputs being denoted as inverse and the explanation of the invalid state. This part gets glossed over in many other people's explanations (probably because they don't have a very deep understanding of the thing they are attempting to explain). Thanks again
The animation of the highs and lows are what really helped me understand the concept, great work 🙏🙏
Thank you :)KD
You saved me 6 months of my life. Thank you
How bro?
@@xeyutipe our professor couldn't teach for shit. This video helped a lot.
@@Behdad47 did you finish college yet?
@@xeyutipe Nearly done. I hit rock bottom in my life exactly two years ago and still have a few courses to finish.
Wow! I couldn't understand this latch until this video. Thank you so much for your great job!
Great Educational video. Comprehensive and clear explanation. Thank you for taking the time and for the quality.
Wow - a bunch of years later and these videos are still fun 🙂
Yes - still relevant. Thank you :)KD
Great video! I have already learned the function of SR latch, but I was confused by different realizations of the circuit which are perfectly explained here.
This video is absolutely great
Thank you so much :)KD
Thank you so much, your video helps a lot. My textbook didn't explain the nor gate and the nand gate well like you did and I came across to your video that I am start learning the flip lops and latches. This video is very great!
I'm very happy to help :)KD
You've got a subscriber mate, You are wayyyy better than my teacher, and your explanation directly goes to the permanent area of brain. Great Job, well done, God Bless You!!!!! Keep up the good work!
Thanks for the lovely comment. Please spread the word about my channel. :)KD
My subject teacher explained it five times, but this one time explanation is worth more than that of five times. :)
Had this in an hour lecture the other day and understood nothing. So glad i found your channel.
Glad to be of assistance. :)KD
This explanation is perfect! Better than my Digital circuits course that I pay $700 for
Found the reason that such pointless sites continue to exist LOL
Did you make a mistake 8:52 when you said that the SR input are held high? Because isn't the NAND logic latch are active low like you said at 10:22 later?
These video's are very good. You are helping me through Uni! Thanks!
I'm delighted to be of service. Thanks for commenting :)KD
This is a great series of videos on latches & flip-flops!
At 3 minutes and 21 seconds into this video how exactly does someone know that the top output is a 1? When what you need to know is that the top input of the set inputs OR gate is a one when bottom input of the reset OR gate needs to be know first to know that.
In real life, it's startup state is considdered random. Because any of the two states is determined by wich nor gate is stronger than the other to force a 1 on the output. It's why whenever a cpu starts up all registers need to be reset and put in a known state for it to function propperly. In the video he assumes the top one is set because it helps make the explination simpler.
I have a similar question. How do you know that both of the inputs for the top gate are 0 when the second input of the top gate is dependent on the output of the bottom gate, which is in turn dependent on the output of the top gate? It seems paradoxical. Clearly I'm missing some unspoken rule on the ordering or just misunderstanding something?
The starting state is determined at the moment the power suplied. its random Q can be either 1 or 0. but once its determined the the other become imedeately the opposite of that .
Thank you for your interrogation I was so lost at that level
Dude my teacher is so ass. He starts talking to us like we already know this stuff. Thank you for the video
You're welcome :)KD
Explained in a nice easy to understand way really well, thanks very much! Wish I just watched this video first instead of wasting hours of reading my textbook
It's great to know it was useful. Thanks for commenting.
i was thinking of getting my degree abroad .Thank god i didnt .Thanks dad for not letting me
This video helps me have a deep understanding about SR Latch than I watch my video of professor
you sir are a life saver...pls continue this awesome work.you are so helpful...probably more than you think
Thank you. You're very kind :)KD
this is really good, with clear explanations and the animation used well
Very well done lesson.
One of the sources of confusion is that the two gates are drawn in parallel. This is elegant but makes it harder to work out the series of events.
Just redraw the circuits as two gates in series and it becomes easier to see the positive feedback path and then to visualise the timelines.
Sounds like a good idea. Next time I teach this to a class, I will ask them to redraw the circuit in the way you suggested :)KD
at 3:28, why is the top nor already producing an output but the bottom one isn't? the setup is symetric, so both should be on instantly, then switch each other off and on again in an endless loop.
Propagation delays which depend on external conditions mean that it is highly unlikely both inputs will be set to low at the same time (and it's low voltage that represents 0, not no voltage). Nevertheless, the circuit will reach equilibrium as soon as a pulse is applied to just one of the inputs. :)KD
@@ComputerScienceLessons so the starting state is random?
your video is so good that even my teacher asked us to watch this video instead of teaching about it in class
These videos are the absolute best
Tnx :)
Thank you so much for this easy to follow explanation! My professor has zero interest in actually teaching lessons in class and just tells us to read the text book. I might actually pass this class now😅
Delighted to help. :)KD
mate, i dont know how but you made this so incredibly simple for me to understand. kudos
Those who are confused, Q= House of 1 & Q°= House of 0.
Therefore, if Q has a value of "1", the Latch stores 1. It's because Q is the House of 1.
And, if Q° has a value of "1", the Latch stores 0. It's because Q° is the House of 0.
One doubt at 3:27 ... initially how can u consider Q is high? bc for the top NOR gate, one input is R=0 and other one is not defined right? it is the output of bottom NOR gate who's one input is output of top NOR gate.. damn i feel like inception
Thank you very much. As said below this video gives a clear and concise explanation. I do appreciated the illustrations, they are excellent.
Thanks for the kind comment :)KD
Thank you very much, this part was really difficult to understand well before this video
Thank you so much for this explanation. Some electrical engineering students are are more confident now because of this video. I know I am
You are most welcome. Thanks for the comment :)KD
Very concise explanation. Great work sir, thank you!!!
I needed this playlist. Thank you so much!!!!! LIFE SAVER!!!
thanks man, you saved my GPA
Thank you for the practical application at the end!
This is my favorite video, it puts me to sleep at night!
I've been putting students in my classroom to sleep for years. Perhaps I'll start a channel of bedtime stories.
Although I don't like typical latch circuits your videos still seem accurate
Thank you for explaining it so simply!
You're welcome :)KD
Can we put complements on inputs (both S and R inputs) to make it 'active high' SR NAND latch?
So, the startup first states actually does not matter. The only thing that matters here is which input has an effect on which output. :D Brilliant !!
Indeed! :)
For active low latch, do the S and R normally have a pulse and then to make a change you remove a pulse? Or do they not normally have a pulse and you provide a low pulse to make a change?
great video great explanation of the application of the latch with the button example
This is immensely helpful, thank you!
Great videos, hope you keep making more playlists.
Moe on the way soon
Why do you assume the outputs for Q and Q complement at 3:16? Who's to say that Q has to be high? I don't understand why it's just assumed to be that way.
yes
why i dont get it
Great video! It helped me understand latches just fine . The example at the end was great. It is definitely amazing what simple binary logic can do !
I think this video slowed down from 1.25 speed, feels like it suits you better. Great content.
you're amazing, Mr. Kevin.
Thank you, the video really helped. My problem was how it could work if they both simultaneously need input from the other
You are welcome :)KD
With NOR SR latch, I don't understand how the gates can output a signal initially. You need two input signals for the NOR gate but initially there is only one input for each of the NOR gate (R and S) since the Q and NOT Q outputs are not generated yet. Can NOR gates output a signal given only one input signal?
This helped me out greatly on a project, thank you very much!
You're very welcome :)KD
Really commendable job!!! Keep Rocking!!! Saw this video, and immediately subscribed!! I like the way you approached the topic. Great for beginners. Thanks a ton for this!!!
Thanks for the great comment. Still rocking. :) KD
Hayst this pandemic.
Thank you very much for creating this video ❤️
My pleasure :)KD
Thanks so much!!
I felt like in a scene in Snatch and Jason Stateham teaching me digital electronics
It's not a tickling competition. :)KD
@@ComputerScienceLessons it's an unlicensed boxing match!
:D
I didn't understand what happens when q=0, because of the nand logic ports, should it be invalid when E=0?
Have you watched the second video in this series yet, The Gated SR latch? This is when I introduce E? :)KD
Well, I have always considered the latches as some sort of electronic toggle switches. If the leaver is up the input is one, when the leaver is down, the input is the opposite. So it's like the electronic equivalent of a mechanical toggle switch
Better than my professor
The hardest part how cross linking works is unexplained.
Clear explanation and visualization. Thank you!
Thank you for making this video. My professor is terrible at explaining these latches.
Good luck for your exam :)
thannk u very much this helped me in my practical exams
Delighted to help :)KD
the thing is: the output differs depending on whether we start by outputing S, then transferring its output to an input of the NOR gate with R or outputing R then transferring the output as an input with S. Like for the first SR Latch made of NOR gates, assuming S=0 and R=0 If we start with S=0, Q'=S=0 then (R+Q')'=(0+0)'=1 so Q=1 BUT if we start with R, it flips: R=0, Q=R=0 then (S+Q)' = (0+0)'=1 so Q'=1. Completely different answers. So, which is the dominant path here?
or do we just treat the whole circuit as a single NOR gate, since S=0 and R=0, (S+R)'=Q, so Q=1 and in turn the inverse of Q will then be 0 ??
You're absolutely right. This used to bother me because I overthink things. The way i see it, the answer is: race condition. Basically, both results are valid, as seen in the truth tables at 10:01 . You don't care whether Q or Q' is set. All you care about is the fact that they are opposite. After all, this is a Set Reset latch, so you can put it into a favorable default state if it initializes into an undesirable state. As long as R and S do not violate the one illegal condition for whichever latch, you will have a latch that initializes into one of two states, which can be adjusted by the inputs as needed. To answer your question explicitly, there is no dominant path. It all depends on the propagation delay of the components.
@@mikey.audio. I overthink too. Thank you for your simple but effective answer. It clears my doubts and persuades me to deal with the question later when I learn more about the delay.
hi from Costa Rica , excelent video! +10
Hi in Costa Rica. And thanks :)KD
i learned more form this video than my class in college
Thanks for the comment. :) KD
@@ComputerScienceLessons no m8, i thank YOU because you just helped me on my test three days ago
Thank you so much. I hated my digital logic class because of latches and flip flops.
Wow, a really good explanation. Thank you
You're very welcome :)KD
Just amazing both the animation and the explaining
This better than my 2 hour lecture
Glad to help :)KD