In the last example of gated SR latch with clock here sir use SR latch having NOR Gate and S corresponds to Q' & R corresponds to Q . that's why it is confusing sir, not mentioned it. Now what it again you can understand.
In Gated SR latch using NOR, when E=1 and S,R =1 then you have said that the case is forbidden, but the inputs that are given are R' and S' so S,R = 0 must be forbidden? Also, The truth table for both Gated SR latch using NOR and NAND is same whereas it is different for SR latch using NOR and NAND? could you explain both these doubts.
12:33 is the truth table correct?? coz when s is 1 and r is 0 Q shall be 1 and R shall be 0...we can see when s' is 1 and r' is q is 1 on gated switch which has same nand gate..
This is a truth table of the SR latch with active low inputs. That means S = 1 and R = 0, it will reset. That means Q = 0. (In active high SR latch, when S = 1, R = 0 then Q = 1)
you said the inputs for sr transparent latch(using nand gates) are active low inputs and others are active high inputs.does this active low or high inputs have any correlation with the outputs we get (Q and Qbar).would you clarify this. its confusing
No, only inputs are active low. Consider the output as it is. For example, to set Q = 1, here for active low inputs S should be 0 and R should be 1. And likewise to reset the latch, S should be 1 and R should be 0. I hope it will clear your doubt.
can i ask a doubt? why S and R have different timing.. sometime it has very duration.. sometime low. I am not an electronics student. its my complementary sub. so do you think is there something I needed to know? the timing is 26:48
Both S and R are different inputs. Many times in a bigger circuits, these inputs are the output of some other circuits. So, they may not be a same. That is why, if you see a time domain signal, then you may notice that, both S and R inputs are changing at the different times. I hope, it will clear your doubt.
Here we are assuming that, initially both S and R is 0. Now, when S is 1, then output of the first NOR gate becomes LOW. So, A = 0. And R is also 0. That means the output of the second NOR gate will become 1. And that's why B = 1. I hope, it will clear your doubt.
Sir, Need derivation or source of diagram of SR latch because of confusion: Short connection from NOR gate A to NOR gate 2 vs Connection from NOR gate 2 to NOR gate 1.
Active High means the input pin or the input signal will be active when that input is Logic '1'. (the input is active when its logic level is 'High') In the active low , the input pin or the input signal will active when that input is logic '0'. (Input is active when its logic level is 'LOW') I hope, it will clear your doubt.
It is assumed that, both S and R are 0 initially. And when S becomes 1 momentarily then both A and R will be 0 and hence B becomes 1. I hope, it will clear your doubt.
Very very thank you for this awesome lecture. Everything came naturally one after another.
I appreciate hearing the word circuit now unlike others they were pronouncing as cirkyut...
thankyou sir you made the concept crystal clear
Exelente explicación. Muchas gracias!!!
Thank you sir for making it premier so that we can ask you anything as you are available here
Please continue such informative and useful vedios,God bless you
Excellent explanation
Excellent explanation sir 👌😌
Well explained.. And very clear.
thank you so much
In the last example of gated SR latch with clock here sir use SR latch having NOR Gate and S corresponds to Q' & R corresponds to Q .
that's why it is confusing sir, not mentioned it.
Now what it again you can understand.
3:55 the output should be low instead of high, otherwise very good explanation, keep it up! 😁
Great 👏👏👏👏👏
Great concept sir
❤️❤️❤️
well explained...keep continue to upload so more videos i will support you dear😊
In Gated SR latch using NOR, when E=1 and S,R =1 then you have said that the case is forbidden, but the inputs that are given are R' and S' so S,R = 0 must be forbidden? Also, The truth table for both Gated SR latch using NOR and NAND is same whereas it is different for SR latch using NOR and NAND? could you explain both these doubts.
See the terminal brother...
R output is Q not equal to R output is Q'
Thanks for sharing with us. Can you tell me which software did you use for drawing timing graphics?
Sir while applying inputs to combinational ckt is there any order to follow like msb to lsb or lsb to msb
i'm totally confused now
How about now?
Same here bro
5 months up... Now?
Are you alive now
He had massive ACCIDENT while studying in car... RIP 😔
Sir, gated sr latch timing and level triggered flip flop. Are both same or is there any difference
12:33 is the truth table correct??
coz when s is 1 and r is 0 Q shall be 1 and R shall be 0...we can see when s' is 1 and r' is q is 1 on gated switch which has same nand gate..
This is a truth table of the SR latch with active low inputs. That means S = 1 and R = 0, it will reset. That means Q = 0. (In active high SR latch, when S = 1, R = 0 then Q = 1)
3:04 explain about this 2 way switch
you said the inputs for sr transparent latch(using nand gates) are active low inputs and others are active high inputs.does this active low or high inputs have any correlation with the outputs we get (Q and Qbar).would you clarify this. its confusing
No, only inputs are active low. Consider the output as it is. For example, to set Q = 1, here for active low inputs S should be 0 and R should be 1. And likewise to reset the latch, S should be 1 and R should be 0. I hope it will clear your doubt.
can you please provide slides
can i ask a doubt? why S and R have different timing.. sometime it has very duration.. sometime low. I am not an electronics student. its my complementary sub. so do you think is there something I needed to know? the timing is 26:48
Both S and R are different inputs. Many times in a bigger circuits, these inputs are the output of some other circuits. So, they may not be a same. That is why, if you see a time domain signal, then you may notice that, both S and R inputs are changing at the different times.
I hope, it will clear your doubt.
Hello sir at 3:56 how when S=1 then B=1!
Here we are assuming that, initially both S and R is 0. Now, when S is 1, then output of the first NOR gate becomes LOW. So, A = 0. And R is also 0.
That means the output of the second NOR gate will become 1. And that's why B = 1. I hope, it will clear your doubt.
Sir what about finite state machines kindly please do that video too
FSM will also be covered soon.
Sir, Need derivation or source of diagram of SR latch because of confusion:
Short connection from NOR gate A to NOR gate 2 vs Connection from NOR gate 2 to NOR gate 1.
Hello sir,
Could you just explain what is active high and active low in brief? because it is getting hard to interpret these words
Active High means the input pin or the input signal will be active when that input is Logic '1'. (the input is active when its logic level is 'High')
In the active low , the input pin or the input signal will active when that input is logic '0'. (Input is active when its logic level is 'LOW')
I hope, it will clear your doubt.
A=0 when S=high
But How is B=1 when S=high @3:47
It is assumed that, both S and R are 0 initially. And when S becomes 1 momentarily then both A and R will be 0 and hence B becomes 1. I hope, it will clear your doubt.
@@ALLABOUTELECTRONICS okay thank you
kuch samajh nhi aaya
Watch some non- indian accent. This is important to your learning too. WTF