Yours is probably the most easy to understand, clear introduction to these things, your videos are immensely appreciated. But a lot of items are missing from the playlist. Why did you stop making these videos? Please continue.
I cannot express to you how frustrating my Digital Systems class has been. I've been watching your videos for weeks now and I am grateful because you are relating the material in such a clear and simple way that I am grasping these foreign concepts. My course videos were done by a instructor so monotone-- it's like nails on chalkboard. Your voice (and accent) is musical. Thank you so much!
A word of warning if you do the OCR A Level specification... For this course you are required to understand the behaviour of what they refer to as a 'D Type Flip Flop'. If you look at the mark schemes for practice papers, you will see that as far as OCR are concerned a Gated D Latch and a D Type Flip Flop are one in the same. My favourite A Level textbook by Heathcote and Heathcote is in agreement with OCR; The text book refers to a Gated D Latch as a D Type Flip Flop. Arguably, my fifth video is about the 'Master Slave D Type Flip Flop', and 'D Type Flip Flop' is another name for a Gated D Latch. If OCR ask you for a timing diagram for a D Type Flip Flop, give them one for the Gated D Latch (it's simpler, the output follows the input if the clock is high). Sorry if I have blown your mind! If you do one of the other exam boards, make sure you understand their specific terminology.
Two days struggling with this!!!!!! I wished I had found this mini-course much earlier, or rather, that my professor had spared us the lecture and addressed us to here. Thank you!!!!
I recently graduated from electrical engineering - after several co-op terms and internships and digital logic classes, I just now understood what master slave meant. Thank you!
I have the same thought. I'm dumping 5 years worth of savings into a degree where i do 99% of my learning on youtube. Sadly youtube cannot certify engineers... yet.
As a former teacher myself, I agree. I decided to enter the industry after leaving an adjunct position because 1) I wanted money, and 2) I couldn't, on good conscience, teach the same exact material as found in these type of videos, knowing that my students were thinking "why am I paying for this?" and quite possibly getting more out of the video than from my lectures. At the risk of pissing off the department, I did spice things up by taking some detours, such as explaining the internals and operation of CMOS Inverters and NOR/NAND gates, but I had to be selective with these kind of lessons since it wasn't part of the curriculum for these low-level combinational and sequential logic courses. The best way to differentiate academia from youtube is to have awesome lab courses with access to equipment and software that a student couldn't possibly afford, but I'm surprised at how many universities only have one or two labs in their entire EE curriculum.
I can't help but say thank you for making the videos on flip flops and latches. They helped me a lot in trying to grasp the concepts that's not very easy to understand (especially in distinguishing between the various types of flip flops and latches).
@@ComputerScienceLessons Sorry for the sudden question but is it right to say that this master slave flip flop has the same behaviour as a negative edge triggered pulse latch?
Thank you so much for these incredibly amazing videos! I've been slaved to logic gates for weeks and your explanation is the most informative and the clearest. Could you PLEASE make more of this series like T flip-flop or JK flip-flop, and their confusing applications like counter, multiplexer, shift register, decoder? These videos are highly appreciated and thank you again for the effort you put into these.
I love you my man! This was so clear and to the point! I have been trying to find videos that can help me understand this stuff and you did! Cheers to you man!
Could you continue these lessons and go into plexers, J-K flip flops, programmable memory, registers, counters, and FSMs, please? These hour's worth of videos have made better use of the lectures given to me over the course of two weeks. I need more! =]
I've had a few requests to do some more along these lines. I really enjoyed making them so will return to electronics one day. In the meantime I am making some JavaScript videos for my own students. Thanks for the lovely comments. Your own UA-cam channel looks interesting. :)
there's good video on jk on neso academy channel. T flip flops are pretty much jk but you give same input in place of j and k. Making 0 = memory; 1= reverse. (unlike D where one input is reversed making 1 = set; 0 = reset)
Very good video's and explainations I can follow all of it, although I got it on school too.. but these video's really help me to understand it even more! I hope you can/will make more video's later on! greetz from Holland!
You might like my version of a data flipflop. It has a input , display output, and output. Initially (and anytime the display output is low) what is at the input is at the display output. When the clock goes high the display output is transferred to the output and the input is transferred the display output. When the clock goes low the output goes low. I don't use my data flipflops for counter circuits
Thank you Thank you God bless you. Man, my instructor has a heavy accent and sucks at teaching. You are awesome. Please keep making more videos. I appreciate it.
The thing i don't understand is, that this appears to only fix glitches that start before the lead edge of the clock pulse, if the glitch occurs during clock high and finishes when clock low (which could be a relatively small glitch), it will be recorded?
although it's the best lecture about flipflops on yt but still you could have made truthtables at each stages and a little bit more enhanced animation instead of changing all at once it could have been better but anyways, it's better than my college
I don't quite understand, why not to work with the device from the previous video, a D latch where D is sampled on the rising edge of the clock ? (in this video we have a regular clock, no little triangle in front of C input) Wouldn't this solve our problem of Q not changing while we sample it ? (I assume this is the problem that the Master Slave Flip Flop is trying to solve)
Very good videos, thank you for that! One thing is not entirely clear however, would be glad if someone can clear this up: In order for this to be really glitch-free, we have to assume that the low clock signal arrives at the slave before Qm is computed. In other words, the propagation delay of the clock signal to the slave has to be shorter than the propagation delay from D to Qm, otherwise the glitch can pass to the slave. Any ideas how that is guaranteed?
Surely there's a chance that a very short glitch in D could propagate to Qs if it occurs just as the clock goes from 1 to 0? It doesn't seem very useful in terms of ignoring glitches to me if this is the case.
Are master/slave D flip flops the building blocks of shift registers? This would prevent bits from latching to a higher bit and throwing the entire sequence out of whack.
and here's the online simulator for experimenting this, www.falstad.com/circuit/e-masterslaveff.html By tapping on H in D line you can change the signal.
You have jumped in at the deep end. You should review logic gates and logic gate combinations first (take your time if they are new to you). Then watch the whole series on latches and flip flops in order. It will take some time. :)KD
This is the gold standard for recorded lessons - covers everything without a single unnecessary word. Thank you so much.
Thank you so much :)KD
Yours is probably the most easy to understand, clear introduction to these things, your videos are immensely appreciated. But a lot of items are missing from the playlist. Why did you stop making these videos? Please continue.
You teach in such a satisfying way, I had so many "oh yeah!" moments watching this series
This series literally saved me!! Thank you so much for the clear and in-depth explanations!!!
You are most welcome :)KD
amazing! my lecturer for hardware verification doesn't bother to explain this and this playlist makes it sooo clear! just what I needed.
You're most welcome Thanks for the comment :)KD
I cannot express to you how frustrating my Digital Systems class has been. I've been watching your videos for weeks now and I am grateful because you are relating the material in such a clear and simple way that I am grasping these foreign concepts. My course videos were done by a instructor so monotone-- it's like nails on chalkboard. Your voice (and accent) is musical. Thank you so much!
watched the whole playlist. saved my life.
you are a god amongst men.
A word of warning if you do the OCR A Level specification... For this course you are required to understand the behaviour of what they refer to as a 'D Type Flip Flop'. If you look at the mark schemes for practice papers, you will see that as far as OCR are concerned a Gated D Latch and a D Type Flip Flop are one in the same. My favourite A Level textbook by Heathcote and Heathcote is in agreement with OCR; The text book refers to a Gated D Latch as a D Type Flip Flop. Arguably, my fifth video is about the 'Master Slave D Type Flip Flop', and 'D Type Flip Flop' is another name for a Gated D Latch. If OCR ask you for a timing diagram for a D Type Flip Flop, give them one for the Gated D Latch (it's simpler, the output follows the input if the clock is high). Sorry if I have blown your mind! If you do one of the other exam boards, make sure you understand their specific terminology.
please continue the series man
Two days struggling with this!!!!!! I wished I had found this mini-course much earlier, or rather, that my professor had spared us the lecture and addressed us to here. Thank you!!!!
I recently graduated from electrical engineering - after several co-op terms and internships and digital logic classes, I just now understood what master slave meant. Thank you!
You are a gifted individual indeed. More power to you sir!
You're very kind. Thank you :)KD
best videos about flipflops and latches ive found so far. very nice!! thnxxx!!!
You are most welcome. Thanks for the lovely comment :)KD
Please do a video on the *JK flip flop* and the *T flip flop* as well. Thanks!
11:37 time to bust out the belt
i laught harder than i should've
took me a sec to understand it omg XD
LMAOOOOOOOOOOO
I feel like I'm listening to a narration of a novella 😂😂 You have an incredible voice! Gets me interested in what I'm learning.
Lovely comment. Thank you. :)KD
Thank you my prof. I wonder why we pay universities and end up having a perfect lecture on UA-cam
I have the same thought. I'm dumping 5 years worth of savings into a degree where i do 99% of my learning on youtube. Sadly youtube cannot certify engineers... yet.
As a former teacher myself, I agree. I decided to enter the industry after leaving an adjunct position because 1) I wanted money, and 2) I couldn't, on good conscience, teach the same exact material as found in these type of videos, knowing that my students were thinking "why am I paying for this?" and quite possibly getting more out of the video than from my lectures. At the risk of pissing off the department, I did spice things up by taking some detours, such as explaining the internals and operation of CMOS Inverters and NOR/NAND gates, but I had to be selective with these kind of lessons since it wasn't part of the curriculum for these low-level combinational and sequential logic courses. The best way to differentiate academia from youtube is to have awesome lab courses with access to equipment and software that a student couldn't possibly afford, but I'm surprised at how many universities only have one or two labs in their entire EE curriculum.
This series is fantastic.
I can't help but say thank you for making the videos on flip flops and latches. They helped me a lot in trying to grasp the concepts that's not very easy to understand (especially in distinguishing between the various types of flip flops and latches).
Glad to help :) KD
@@ComputerScienceLessons Sorry for the sudden question but is it right to say that this master slave flip flop has the same behaviour as a negative edge triggered pulse latch?
Thank you so much for these incredibly amazing videos! I've been slaved to logic gates for weeks and your explanation is the most informative and the clearest. Could you PLEASE make more of this series like T flip-flop or JK flip-flop, and their confusing applications like counter, multiplexer, shift register, decoder? These videos are highly appreciated and thank you again for the effort you put into these.
Keep up the great work! Don't know how I would pass any exam just by the explanations provided by my university.
:)
thanks a lot sir, you saved many lives!
Excellent speech articulation. Very clear speech.
It is very likely to use your name in my Thesis. I will mention you as an informative source.
Sounds great. Thank you. :)KD
Thank you so much, this is very helpful!
Oh man this is so marvellous fantastic I would love to see more videos of it, specially about asinchronous counters.
I love you my man! This was so clear and to the point! I have been trying to find videos that can help me understand this stuff and you did! Cheers to you man!
Excellent explanation, thanks from Argentina!
Could you continue these lessons and go into plexers, J-K flip flops, programmable memory, registers, counters, and FSMs, please? These hour's worth of videos have made better use of the lectures given to me over the course of two weeks. I need more! =]
I've had a few requests to do some more along these lines. I really enjoyed making them so will return to electronics one day. In the meantime I am making some JavaScript videos for my own students. Thanks for the lovely comments. Your own UA-cam channel looks interesting. :)
Computer Science Thank you kindly!
VERY INFORMATIVE TUTORIAL, THANK YOU!
You are most welcome :)KD
Exam in 1 hr 20 mins. Your videos will save me.
I hope the exam went well :)KD
Just amazing. Many thanks ❤
Thank you very much for your help!
thank you very much for such a great series of videos
Really helpful. thanks!
You're welcome :)KD
Thank you so much sir....Your way of explination is really superb.../\...
Tnx. K:D
Many thanks from romania :*
Very helpful as a computer engineering student, please make more videos
It's awesome !!! I finally understand!
This was great!
What a masterpiece lecture.
I appreciate the comment. Thanks. :)KD
hatur nuhun braaay . Many thank's from bandung
DO JK and T TYPE FLIP FLOPS PLEASEEEE!!!!!!!!!!!!
there's good video on jk on neso academy channel. T flip flops are pretty much jk but you give same input in place of j and k. Making 0 = memory; 1= reverse. (unlike D where one input is reversed making 1 = set; 0 = reset)
Very good video's and explainations I can follow all of it, although I got it on school too.. but these video's really help me to understand it even more! I hope you can/will make more video's later on! greetz from Holland!
thank you. it is clear and easy to follow.
:)
Thanks man you a real one
Thank you so much
You're very welcome :)KD
this is a great video! :)
You might like my version of a data flipflop. It has a input , display output, and output. Initially (and anytime the display output is low) what is at the input is at the display output. When the clock goes high the display output is transferred to the output and the input is transferred the display output. When the clock goes low the output goes low. I don't use my data flipflops for counter circuits
Thank you Thank you God bless you. Man, my instructor has a heavy accent and sucks at teaching. You are awesome. Please keep making more videos. I appreciate it.
You completed an awesome work explaining the SR and D type latches but why did you not continue with an explanation of the JK flip-flop?
Thank you. I plan to add to this playlist, one day :)KD
The thing i don't understand is, that this appears to only fix glitches that start before the lead edge of the clock pulse, if the glitch occurs during clock high and finishes when clock low (which could be a relatively small glitch), it will be recorded?
You're awesome!
And so are you :) Tnx
Awesome content. I got all my doubts cleared regarding this topic. Sir can u tell the source or book which u follow.
although it's the best lecture about flipflops on yt but still you could have made truthtables at each stages and a little bit more enhanced animation instead of changing all at once it could have been better but anyways, it's better than my college
Great help thank you so much
Maybe you would be interested in the D flip flop I used as a result of having forgot the conventional D flip flop
I don't quite understand, why not to work with the device from the previous video, a D latch where D is sampled on the rising edge of the clock ? (in this video we have a regular clock, no little triangle in front of C input)
Wouldn't this solve our problem of Q not changing while we sample it ? (I assume this is the problem that the Master Slave Flip Flop is trying to solve)
2:49 Game players explaining to the game developers what they really think the new features are
Very good videos, thank you for that! One thing is not entirely clear however, would be glad if someone can clear this up:
In order for this to be really glitch-free, we have to assume that the low clock signal arrives at the slave before Qm is computed. In other words, the propagation delay of the clock signal to the slave has to be shorter than the propagation delay from D to Qm, otherwise the glitch can pass to the slave. Any ideas how that is guaranteed?
" . . . the master behave exactly like a Gated D Latch . . . . well of course it does, BECAUSE THATS EXACLY WHAT IT IS."
I love you.
😳 :)KD
What if raising edge of clock pulse in master flipflop is in metastable state with falling edge of clock pulse in slave flipflop??
pseudo code for slave Q:
for each fall of C:
continue Q with adding one cycle of state(D) //state(D) is either high or low at that time of measuring D
Thanks!
Surely there's a chance that a very short glitch in D could propagate to Qs if it occurs just as the clock goes from 1 to 0? It doesn't seem very useful in terms of ignoring glitches to me if this is the case.
can I use the master/slave (version nand gate) to make a divide by 2 counter by feeding Qbar slave output to D master?
Are master/slave D flip flops the building blocks of shift registers? This would prevent bits from latching to a higher bit and throwing the entire sequence out of whack.
I would have never understand that by my own lol(too complicated). Thx
idont konw how can i thank u
but i have a qustion that if we have multi inputs like s1,s2,s3
and r1,r2,r3 linked with preset and clr in and gat
and here's the online simulator for experimenting this, www.falstad.com/circuit/e-masterslaveff.html By tapping on H in D line you can change the signal.
This is racist
microphone upgrade!
I have a new mic now, along with a boom arm and a suspension mount. It seems to make a difference to my latest videos :)KD
I don't understand this video.
You have jumped in at the deep end. You should review logic gates and logic gate combinations first (take your time if they are new to you). Then watch the whole series on latches and flip flops in order. It will take some time. :)KD