Sir in video u have connected body p+ and body n+ to Vss n vdd respectively thn how does lactup occur still??..since to avoid latch up v r using well tap which gives same vdd n Vss connections.
Hi Santosh, Thanks for raising a very good point. I would like to say in this regard, Well taping is a way to prevent Latch-up, and well taping in nothing but connecting N+ well and P+ Substrate to VDD and VSS respectively. But in this example, I have tried to establish that there is such connection but these are not sufficient enough that's why emitter-base junction of parasitic BJT gets forward biased. If the well is sufficiently tapped, the drop to the base ( which is in well) will not be high enough to make for emitter-base junction forward biased (cross the barrier potential). Thanks.
@@TeamVLSI thanks a lot sir ur reply helpd.. and i hav found ur videos vry useful sir... Thy stand apart from rest of UA-cam VLSI videos plz keep uploading more content sir.. thanks a l Ton sir __/\__
Can you please add this point when u uploading a video to prevent latchup -“how latch up is prevented by adding tap cells on core with particular distance.”
Thank you Bindu for your valuable suggestion. I have already planned to cover at least two latch up prevention techniques, tap cells and guard ring. Thanks you again for right suggestion at right moment. I will try to address you concern.
Very Good lecture. easily can understand if one knows operation of diode well
Thanks Krishna.
Very good explanation..! Sir
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Keep watching for lots of such available tutorials and many to come. Keep supporting the channel.
Sir in video u have connected body p+ and body n+ to Vss n vdd respectively thn how does lactup occur still??..since to avoid latch up v r using well tap which gives same vdd n Vss connections.
Hi Santosh,
Thanks for raising a very good point.
I would like to say in this regard, Well taping is a way to prevent Latch-up, and well taping in nothing but connecting N+ well and P+ Substrate to VDD and VSS respectively. But in this example, I have tried to establish that there is such connection but these are not sufficient enough that's why emitter-base junction of parasitic BJT gets forward biased.
If the well is sufficiently tapped, the drop to the base ( which is in well) will not be high enough to make for emitter-base junction forward biased (cross the barrier potential).
Thanks.
@@TeamVLSI thanks a lot sir ur reply helpd.. and i hav found ur videos vry useful sir... Thy stand apart from rest of UA-cam VLSI videos plz keep uploading more content sir.. thanks a l
Ton sir __/\__
hey!! Can you make a video on scan chain??
Excellent work sir. From you only i understand this topic very well.Thank you sir .
Can you put any pdf for this?
👏👏👏👏👏
Thank you.
Can you please add this point when u uploading a video to prevent latchup -“how latch up is prevented by adding tap cells on core with particular distance.”
Thank you Bindu for your valuable suggestion. I have already planned to cover at least two latch up prevention techniques, tap cells and guard ring.
Thanks you again for right suggestion at right moment. I will try to address you concern.
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Yes we have started a new group recently.
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Thank you!!
I am a beginner in this field, currently pursuing Mtech in VLSI 1st year
Any tips, suggestions or advice for me .
Be connected with us, and ask doubts in group.
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Thank You .
Awesome
Thanks Sameer.
Happy learning!
Thank you so much sir
You are welcome. :)
thank you sir
I don't know why but I still did not understand despite my sincerest efforts.....
Explanations are not good, pls improve ,not understand what you are saying.
Ok Karthik. I will try my best.
By the way where do you feel difficulty to understand? If any particular point, you can discuss. :)
at triggering mechanism sir
Thank you so much sir
You are welcome @pa1