hi sir, why we take the horizontal layers as m0,m2,m4 and vertical layers as m1,m3,m6 why can't like this horizontal layers as m0,m1,m2 and vertical layers as m3,m4,m5?
Power rangers created around partitions and SoC, but it is not mandatory practice. It is done just for safe side to avoid signals crossing the boundary
While doing power planning we need to make sure of power grid structure. Power grid should be proper and spacing between stripe must be correct to avoid drc. Also power grid should be robust to avoid power drop. Correct stripe should be drawn in correct power domain and we need to ensure that power reached in channel properly to avoid any power failures later
Hi Sir, I have one query in Layout Compaction. While doing 1D Compaction, first we do compaction in either (X or Y Direction) and then in the other direction. So, is that done iteratively or only a single time?
Hi sir, First of all, thank you very much for the course. I enjoyed every minute of your Videos. secondly, I have a doubt if we plan the power for a higher metal layer, how do standard cells get its power, which it planned in lower metal layers? I think we can use vias until we reach to the M1, but this will consume more power and affect reliability, is that true? secondly at what metal layer will be the VDD/GND net/pin exactly? lastly, is it preferred that the metal layer in the Power planning to be vertical or horizontal?
hi sir, why we take the horizontal layers as m0,m2,m4 and vertical layers as m1,m3,m6 why can't like this horizontal layers as m0,m1,m2 and vertical layers as m3,m4,m5?
Sir, how does upf file comes into picture in power planning?
always on and off
retention
voltage transmission l/h and h/l
That ring which you explained, is that only what is called as Guard Ring sir?
@@VLSIAcademyhub oh thank you :)
Hi sir,
The power ring creation is only at chip top or will we create power ring at hierarchical partitions too?
Power rangers created around partitions and SoC, but it is not mandatory practice. It is done just for safe side to avoid signals crossing the boundary
Hi sir,
How to see standard cell rails and via ladders in icc2 and also how to find in in which layer power has been done through gui or shell
Sir how we know in tool a net routed in a particular layer and innovus tool commands for that
While doing power plan...wht issues can we come across d how to resolve
While doing power planning we need to make sure of power grid structure. Power grid should be proper and spacing between stripe must be correct to avoid drc. Also power grid should be robust to avoid power drop. Correct stripe should be drawn in correct power domain and we need to ensure that power reached in channel properly to avoid any power failures later
sir in 5nm technology,
Is Power rings are present?
@@VLSIAcademyhub Thankyou Sir
At which stage standard cell rails are created? Before power planning right!
no after power planning only rails created
Hi sir , How can we decide secondary power regions
Secondary power is one which is not main power for you, you can get it using get_voltage_areas command
sir y u told m6 is vertical as well as horizontal in this video
Any metal layer can have only one direction, either horizontal or vertical.
what was the difference between rail and strap ?
@@VLSIAcademyhub thankq
My I know in which layer these rail and strap will be there??
Sir please explain information regarding tool commands and it practical examples
Sir the layers in the physical design are assigned for the power or they are used for other purposes as well?
yes
Hi Sir, I have one query in Layout Compaction. While doing 1D Compaction, first we do compaction in either (X or Y Direction) and then in the other direction. So, is that done iteratively or only a single time?
@@VLSIAcademyhub Okay no issues.. Will try to get into the topic..
Very explanation sir
Hi sir,
First of all, thank you very much for the course. I enjoyed every minute of your Videos.
secondly, I have a doubt if we plan the power for a higher metal layer, how do standard cells get its power, which it planned in lower metal layers?
I think we can use vias until we reach to the M1, but this will consume more power and affect reliability, is that true?
secondly at what metal layer will be the VDD/GND net/pin exactly?
lastly, is it preferred that the metal layer in the Power planning to be vertical or horizontal?
we will preffered both matel layers