how to check with tool regarding equal spacing , guard rail, or undriven port? Is there some kind of qor report gets generated which provides all details. what is the checkpinassignment command output? does it provide all pin placement coordinates around the core? Gr8 lecture btw , thank you!
The amount of check pin assignment command, is a summary which tells us that how many are legal or illegal ports etc. However it haas switches to provide details of violating port
You said that NDRs can have rules such as 2W, 2S and 2P. But if we double the spacing (S), won't it automatically increase the pitch as well ? I don't understand why 2P needs to be mentioned separately. It would be dependent on the spacing itself, right ?
Minimum Space between core and die is technology specific and above that minimum spacing number we can increase whatever we wish, however it will be waste of space
Deciding core and die area for initial runs is generally derived from legacy design. For a fresh design from scratch, it is generally stdcell area *1.6 for a start, and then it is modified based on requirements
![PD Lec 18- Macro Placement & Floor-planning [part-4] | VLSI | Physical Design](http://i.ytimg.com/vi/AW6OwZxY7VY/mqdefault.jpg)
![PD Lec 18- Macro Placement & Floor-planning [part-4] | VLSI | Physical Design](/img/tr.png)
![PD Lec 15- Floor-planning [part-1] | VLSI | Physical Design](http://i.ytimg.com/vi/Z1Cxbn5LOYg/mqdefault.jpg)
![PD Lec 21- Macro Placement Guidelines Floor-planning [part-7] | VLSI | Physical Design](/img/n.gif)
how to check with tool regarding equal spacing , guard rail, or undriven port? Is there some kind of qor report gets generated which provides all details. what is the checkpinassignment command output? does it provide all pin placement coordinates around the core?
Gr8 lecture btw , thank you!
The amount of check pin assignment command, is a summary which tells us that how many are legal or illegal ports etc. However it haas switches to provide details of violating port
What is the difference between floating pins and undriven pins?
how do we apply blockages and guard rings between core and die? guard rings are applied for latch-up right.
Sir please start tcl script for pd engineer we will join the batch
@@VLSIAcademyhub fee??
How can I join this course?
Hai sir.Can u pls explain the detailed explanation about MMMC file.
Are power pads/ports not included under IO ports ? Sir , are they separate?
Are IO cells and IO pads same thing ? In some places I have noticed IO cells are written?
You said that NDRs can have rules such as 2W, 2S and 2P. But if we double the spacing (S), won't it automatically increase the pitch as well ? I don't understand why 2P needs to be mentioned separately. It would be dependent on the spacing itself, right ?
@@VLSIAcademyhub Got it. Thanks.
how to decide the space between core & die?
Minimum Space between core and die is technology specific and above that minimum spacing number we can increase whatever we wish, however it will be waste of space
Hello , Do you have materials or online courses where i can learn physical design
Hi Sundeep, this series on which you are asking is for learning physical design only
@@VLSIAcademyhub is it possible to get materials for this same PPT content?
how to decide core & die area?
Deciding core and die area for initial runs is generally derived from legacy design. For a fresh design from scratch, it is generally stdcell area *1.6 for a start, and then it is modified based on requirements
on what basis we can say our floorplan is good?
Generally there are checks to qualify your floorplan. Physically speaking, chip integrity checks, grid check, and formality should be enough
Sir, are guard ring and power ring same?
@@VLSIAcademyhub Thanks for the clarification, is it possible to have two ground rings? one for guard and one for power?
dangling port means
Tq sir
Which has no connectivity