PD Lec 23 - Macro placement issues | | Floor-planning | VLSI | Physical Design

[@vinayakbhat415]

How do you take care DRCs while placing macros??
Or what are possible DRCs will see in macro placement ??

[@nehatambe-x7f]

Hi Sir , If macro pins present only on one side , in that case do we need to apply halos on four side?

[@agastinrajece1605]

confused around macro, std cell clamped & Keep out margin

[@430harini8]

Hii sir, why floating macros occurs

[@revansidda2324]

What is congestion issue?

[@punithkumarchinnasani163]

Thanks

[@kiransk4000]

Sir why we can't place macros in core centre only placed in boundry area

[@PrathapTalari-bn6hy]

to avoid the net detouring , we are not place the macros in centre of core

[@alekhyarao4402]

Hi sir
As you said bcz of less channel spacing we got congestion
but how to overcome that issue bcz we can't increase the space
as you said there is no enough space
what we can do

[@alekhyarao4402]

@@VLSIAcademyhub Thank you sir

[@alekhyarao4402]

@@VLSIAcademyhub Thank you sir

[@saisiddarth2104]

I know min space formulae,
Did you what is max spacing between macros

[@saisiddarth2104]

@@VLSIAcademyhub yess I know there is know maximum spacing , but for eg: I have {1500 1500} size ,
Based on the formule min space is 15um but I have given spacing as 70um between the macros because I have enough die size.
If some one asks me why you have gave 70um space ...
can you tell me that what is the good ans I need to give which is acceptable

[@muralikrishna-us1wf]

There is no connection between that two macros and and no conection with same hierarchy macros then 70u is K but is there any conectivity between them are nearby macros then it will be detour , standard cells placed between macros there no plcement blockage,

[@vijay4a4]

Hi sir
is it mandatory to equal channel length between two macros?

[@vijay4a4]

@@VLSIAcademyhub
Ok sir
Thank u