PD Lec 26 - Sanity Checks -1 | Floor-planning | VLSI | Physical Design

[@doxdorian5363]

There's a mistake at the combinational feedback part (around 4:30). The gate should be XOR for the output to oscillate, and not XNOR.

[@vinayakbhat415]

Nice insights !!!.

[@piyushmohapatra4642]

4:04 should be XOR gate for the outputs to toggle

[@jeffrinwilfred1887]

exactly i too got same question

[@piyushmohapatra4642]

@@jeffrinwilfred1887 yep. Don't be confused. What you thought is correct 💯

[@japeshsingla1]

Combinational feedback means loop right?

[@zunaid4664]

When do we do these sanity checks , after floorplanning stage , in the form of post-floorplan checks?

[@bhaskarp125]

are these sanity checks are after floorplan(before placement stage)????????????????

[@lavanyakamsala4883]

Sir can you please tell how can we do in practical

[@VLSIAcademyhub]

Can you tell, What exactly is it that we could explain about practical?

[@kalyanaleti4513]

Can pls share videsh

[@prakashbadhavath4234]

How we check in practical of sanity checks

[@tridibsharma]

Please answer this

[@shrikanthramanagara2382]

Thnk u

[@bhaskarp125]

because of floating input pins how high dynamic power consumption will happen?????

[@bhaskarpalagani3810]

How?