Verilog code(simulation and synthesis) and design of a 4x1 MUX using decoder and buffers

[@euro-lm6gz]

Bahot mst pdhaya sirr itni baar pdh liya tha kabhi smjh na aaya aaj mere sare doubts clr ho gye

[@youngmoney108]

Bro. haven't you studied MAVEN confidential note???? 😄

[@shivanidhiman3975]

there is some error

[@chetu1991]

I think u r from maven silicon right 😊

[@sagarvishwakarma5727]

I think so
Bcoz I am also from maven😅

[@ranadeepgoud0015]

write verilog code for the bidirectional buffer and verify using testbench

[@deepakkumaryadav6009]

Bhi hindi me bole achha se samajh me aa jata .

[@euro-lm6gz]

Best in the world

[@sagarvishwakarma5727]

Bro but u have to blur the name of maven silicon because they didn't gave any permission to use there content anywhere...

[@bindhupriya6033]

i am getting error

[@bindhupriya6033]

can you verify the code