Write a Verilog HDL program in Hierarchical Structural model for 16:1 Mux realization using 4:1 Mux

[@maharshisanandyadav]

www.tmsytutorials.com/write-a-verilog-hdl-program-in-hierarchical-structural-model-for-16x1-mux-realization-using-4x1-mux/

[@tharunkumarbikka9605]

Thank you so much Anna, video chaala useindhi 🙏🫂

[@maharshisanandyadav]

Thanks for letting me know
Check the code from this site
www.tmsytutorials.com/write-a-verilog-hdl-program-in-hierarchical-structural-model-for-16x1-mux-realization-using-4x1-mux/

[@tharunkumarbikka9605]

Anna , RTL for bidirectional buffer, code and text bentch explain chai Anna please

[@maharshisanandyadav]

www.tmsytutorials.com/verilog/

[@baggu8135]

Sir
I'm getting error"mux_2_1 expects 3 arguments"
When I'm performing 4*1 mux using 2"1 mux