Why you are talking about the hold and capture data on next flop 1 period later? As I know you should consider hold violation between same clk edges not a period later, its not a setup check. Please correct me if I'm wrong
Hello, Its a very nice lecture. Very effective and useful. I want to make one correction that in your video, in timing diagram D1 data and Q1 output is looking different. Is it different or same??
+Jay Shah Yes It's Different .. Because For D1 it's input waveform and it can be in any form .. Has no dependency on anyone.. But for Q1 - It's the output of FF1. Has dependency on the CLK_1. When ever there is a positive edge only then D1 input is going to consider. between 1 positive edge to 2nd Positive edge - D1 can change any time.
there are many methods of fixing setup and hold violation. Please refer to my blog 52-ic.com. My blog mainly focus on ic backend design implementation.Thanks.
Use larger/stronger cells to drive paths with high capacitance, which can reduce the time needed to transition on sluggish net. by varying, clock skew(inserting or removing buffers in the clock path). and also by reducing over all clock frequency. propagation delay +clk_to_q delay must be less than or equal to {(time period of the clock)-(set up time of the flipflop)+(clock skew-clock jitter)}.... this inequation must be satisfied.. please correct me if i am wrong
Why you are talking about the hold and capture data on next flop 1 period later? As I know you should consider hold violation between same clk edges not a period later, its not a setup check. Please correct me if I'm wrong
you are right.... this explanation is incorrect.
Yup thats right and even if you consider it to be a setup check, with the skew added it will capture on edge 1 of the capture clock.
Perfectly explained
Hello, Its a very nice lecture. Very effective and useful.
I want to make one correction that in your video, in timing diagram D1 data and Q1 output is looking different. Is it different or same??
+Jay Shah Yes It's Different .. Because For D1 it's input waveform and it can be in any form .. Has no dependency on anyone.. But for Q1 - It's the output of FF1. Has dependency on the CLK_1. When ever there is a positive edge only then D1 input is going to consider. between 1 positive edge to 2nd Positive edge - D1 can change any time.
Thank you for your reply. That FF1 is not D flip flop but its any other flip flop than D is not equal to Q. So its correct. Thank you once again.
Jay .. FF1 is D flipflop.. I will recommend that you check the working of D flipflop once again
+VLSI EXPERT (vlsi EG) Thank you. Now I understand.
very well explained!!
how to fix setup & Hold Violation????
there are many methods of fixing setup and hold violation. Please refer to my blog 52-ic.com. My blog mainly focus on ic backend design implementation.Thanks.
Use larger/stronger cells to drive paths with high capacitance, which can reduce the time needed to transition on sluggish net.
by varying, clock skew(inserting or removing buffers in the clock path).
and also by reducing over all clock frequency.
propagation delay +clk_to_q delay must be less than or equal to {(time period of the clock)-(set up time of the flipflop)+(clock skew-clock jitter)}....
this inequation must be satisfied..
please correct me if i am wrong
in one word:,There should not be negative slack in the circuit.