What is Clock skew? || Types of clock skew . Advantage and disadvantage of clock skew || Explained
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- Опубліковано 6 сер 2024
- Clock skew is explained in this video.
Clock skew Types Positive , Negative , It's advantages and disadvantages.
If you have any doubts in the topic feel free to comment down below, I WILL ANSWER WITHIN 24hrs .
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Very nice explanation. Thank you very much sir.
Thanks for the explanation. With either providing positive skew or negative skew there is always trade-off between setup time constraints and hold time constraints.
Is there any other method to avoid meta-stability wherein both set-up time and hold time constraints can be eased together?
Really good explanation and examples.
Thank you so much fiddler104 🙏
if you need video on any topic if I know that topic I can make a video for you👍
Good Job! Great Video! Thank you so much for your work. I now can understand these concepts.
Your Welcome. Keep Growing:)
Very nice
Superb explaination, you have done it so well , thanks a lot
🙏Namaskaram sir. Always grateful.. great work sir. 👍😊
Namaskaram Jithin, thanks for the support , good luck & great health :)
Good lecture thank you sir
Excellent class sir.. Thank you so much
Namaskaram swarga 🙏, thanks for the support, good luck & great health 👍😊
Good explanation!!
Thank you very much.Appreciate your support. Good luck 👍
Understood....thank you so much
Arigato!! 🙋
Yokoso😀
nice explaination!!!
Thank you so much Bharath, good luck 👍
Can u explain what is absolute clock skew and relative clock skew
Finally i understood
I am glad , I was helpful to you, thank you , good luck, good health 👍
Thank u so much sir
huge respect .
Namaste 🙏 Takveem Khan, thanks for the support, good luck & great health 👍😊
@@KarthikVippala omg so fast sir🙏🙏
🤝
It's to good 👍
Thank you🙏
In case of the circuit without skew, you said output is obtained at second flipflop during tcq+tcombo.. but why didn't you consider the tcq at second flipflop..so that, the output is obtained at Q2, when total time of arrival = tcq1+tcq2+Tcombo..right?
Hey thanks.One doubt -the hold violation occurs because at the same clock edge some previous data is supposed to be stable at FF2 and we are disturbing it with the data from FF1 with recent clock edge ?
Hey Shubham thanks for asking the question,
you have understood it correct.
If you have any more questions please feel free to comment,I am happy to help you , good luck 👍
its not just the combinational delay, its that + tq2c. and also how is your 2nd ff reading the data at the first ff? I strongly believe thats not a good explanation, the 2nd ff is always reading the output of the combinational circuit
thanks
Namaste 🙏 chu ian , your welcome, good luck & great health 👍😊
I didn't get that useful skew in the advantage.. can you explain it?
In hold time which is good positive skew or negative skew?
Namaskaram 🙏 jay, thanks for asking negative skew is good for hold .
Increase the volume bro
will do it upcoming videos
explanation was on point....but one thing I wanted to ask what is this thing that u do with the accent...why u keep changing it😅 and it is very irritating pls drop this🙏
Namaste satyam 🙏, thanks for feedback , I am improving on it , good luck & great health 👍😊
@@KarthikVippala 🙏🙏🙏🙏
hindi
Namaskaram Shubham 🙏 , I will do in hindi for sure in near future, thanks for your suggestion , good luck & great health 👍😊
bina accent ki bhi video baan sakti thi chote
Thik hai bahi, improving on it🙏
bhai kya accent hai yr yeh
sara mood kharab kr rha hai
Improve kar raha hoon bhai