Data types in Verilog | #5 | Introduction | Verilog in English | VLSI

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  • Опубліковано 24 гру 2024

КОМЕНТАРІ • 9

  • @sathyasrirameshkumar23
    @sathyasrirameshkumar23 Рік тому +1

    Please explain port assignments elaborately with example

  • @amudalagopikrishna5745
    @amudalagopikrishna5745 3 роки тому +2

    what is meant by internal net and external net

  • @ajayvala9042
    @ajayvala9042 2 роки тому +2

    What's different between bit[7:0] and byte??

  • @51_sajalgupta84
    @51_sajalgupta84 9 місяців тому

    Mam can you Please Share the whole Notes Please?

  • @Sanjay_Sahu676
    @Sanjay_Sahu676 3 роки тому +4

    Please elaborate lecture......use some general examples applying for this,my opinion is video length is about 10 minutes is fine.....😊

    • @vlsipoint
      @vlsipoint  3 роки тому +6

      I'm providing seperate video for each daratype with examples. For Hindi playlist it has already uploaded and for English playlist it'll be uploaded by this week.

    • @Sanjay_Sahu676
      @Sanjay_Sahu676 3 роки тому +1

      @@vlsipoint That's ok....👍