Nice explanation mam. Mam I have few questions (or Doubts) with me :- 1. In creation of Module which order of ports should be followed?? In Video -3 you explained as (inputs, outputs) In this video we wrote as (output and Inputs) Is there any change in writing of this module by writing in two different ways?? 2. Is giving space b/w declaration ports and assign keywords is mandatory or not? If not why we are giving that space b/w them. Thank you for your efforts mam. 3. Is "indentation" mandatory to follow in Verilog as like as in Python??
This series is really very interesting!!!!
Nice explanation mam.
Mam I have few questions (or Doubts) with me :-
1. In creation of Module which order of ports should be followed??
In Video -3 you explained as (inputs, outputs)
In this video we wrote as (output and Inputs)
Is there any change in writing of this module by writing in two different ways??
2. Is giving space b/w declaration ports and assign keywords is mandatory or not? If not why we are giving that space b/w them.
Thank you for your efforts mam.
3. Is "indentation" mandatory to follow in Verilog as like as in Python??
nice
Mam in this code, where is the c and d inputs.. This code bit confused me.. Can u plzz explain this code..
Hi I want this ppt material where should I get these
You can visit VLSI Point website
@@vlsipoint Can't find the website.
I didnt understand supply0 and supply1 , can you please explain
Madam needs to learn more
Not at all in detail, very very veryyyy basic!!!
Please speak English in all videos