VLSI Physical Design: Clock Tree Synthesis (CTS)

website: www.vlsi-backe...
clock tree synthesis
-Difference between HFNS and CTS
-Why buffer/inverters are inserted?
-Difference between clock buffer and normal buffer
-Inputs of clock tree synthesis (CTS)
-Sanity checks before CTS
-Goals of CTS
-Clock latency
-The clock problem
-Main concerns for clock design: skew, power, noise, delay
-Clock skew: positive skew, negative skew, local skew, global skew, boundary skew, useful skew.
-Clock Jitter
-CTS pre-requisites
-CTS Objects
-CTS Flow
-Clock tree references: boundary cell insertion, delay insertion
-Clock Tree Exceptions: Non stop pins, exclude pins, float pin, stop pin, don't touch sub-tree, don't buffer net, don't size net.
-CTS Algorithm
-Analyze the clock tree
-Post CTS optimization
-CTS outputs
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[@salmaanmohammed3665]

Bhai, You are doing great work. keep posting videos about physical design.. Thank you

[@FerozAhmed_PhysicalDesign]

You're welcome :)

[@nikitak3605]

very nice keep uploading more on pd.thanks

[@harathikondala7098]

In Goals of CTS meeting clock tree targets minimal skew not maximum skew

[@FerozAhmed_PhysicalDesign]

Yes you are correct, it's min skew and min insertion delay.

[@avdheshpalliwal]

Great PPT and explanation dear. Keep it up.

[@bhuvannaga8854]

Is there any explanation in ppt

[@weichung716]

Thanks for the explanation! But I'm not able view the website,can you help to check it?

[@FerozAhmed_PhysicalDesign]

www.vlsi-backend-adventure.in try this, im facing some issue with commercial domain, will switch to com in few days

[@weichung716]

@@FerozAhmed_PhysicalDesign Thanks for the reply! but still can't reach the page when using .in . I will wait for the com page after the fix. Thanks！

[@shrikanthramanagara2382]

Tq

[@FerozAhmed_PhysicalDesign]

Small Corrections :
1. Goals of CTS : targets are min skew and min latency.
2. Global and local skew, in place of flop I said 2 times skew.