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vlsi backend adventure
India
Приєднався 11 гру 2017
VLSI Physical Design Topics
Static Timing Analysis (STA)
Website: www.vlsi-backend-adventure.com/sta.html
Topics
-Timing Analysis
-Difference between Static Timing Analysis (STA) and Dynamic Timing Analysis(DTA).
-Static Timing Analysis- Definition, Main steps of STA.
-STA Inputs and Outputs
-Timing Report
-Clock Storage Elements (transparent latch and Flipflop)
- Delays (Intrinsic, Propagation, Contamination, net)
-Timing ARC
-Timing Unate
-Clock definitions in STA (Synchronous clock, Asynchronous clock, mutually exclusive clock, generated clock, virtual clock)
-Timing Path Groups (In2Reg, Reg2Reg, Reg2out, In2Out)
-Clock latency, Insertion Delay, Clock Uncertainty, Clock skew, Clock Jitter, Glitch, pulse width, duty cycle, transistion/slew.
-Asynchronous path, Critical path, shortest path, Clock gating path, launch path, capture path, Arrival Time, Required Time.
- CRPR(Common path pessimism removal)
-Slack, setup time, hold time, Setup and hold time violations.
-Recovery time, Removal time, recovery and removal violations.
-Single cycle path, Multicycle path, False path.
-Clock crossing domain
-Clock domain synchronization scheme (Pulse width check, Data stability check)
-Bottleneck analysis
-Multi VT Cells (HVT,LVT,SVT/RVT)
-Time Borrowing/Stealing, Time borrowing scenarios,
- Path based STA and Graph based STA.
-Difference between PBA and GBA and Example.
Topics
-Timing Analysis
-Difference between Static Timing Analysis (STA) and Dynamic Timing Analysis(DTA).
-Static Timing Analysis- Definition, Main steps of STA.
-STA Inputs and Outputs
-Timing Report
-Clock Storage Elements (transparent latch and Flipflop)
- Delays (Intrinsic, Propagation, Contamination, net)
-Timing ARC
-Timing Unate
-Clock definitions in STA (Synchronous clock, Asynchronous clock, mutually exclusive clock, generated clock, virtual clock)
-Timing Path Groups (In2Reg, Reg2Reg, Reg2out, In2Out)
-Clock latency, Insertion Delay, Clock Uncertainty, Clock skew, Clock Jitter, Glitch, pulse width, duty cycle, transistion/slew.
-Asynchronous path, Critical path, shortest path, Clock gating path, launch path, capture path, Arrival Time, Required Time.
- CRPR(Common path pessimism removal)
-Slack, setup time, hold time, Setup and hold time violations.
-Recovery time, Removal time, recovery and removal violations.
-Single cycle path, Multicycle path, False path.
-Clock crossing domain
-Clock domain synchronization scheme (Pulse width check, Data stability check)
-Bottleneck analysis
-Multi VT Cells (HVT,LVT,SVT/RVT)
-Time Borrowing/Stealing, Time borrowing scenarios,
- Path based STA and Graph based STA.
-Difference between PBA and GBA and Example.
Переглядів: 14 635
Відео
VLSI Physical Design: Routing
Переглядів 10 тис.4 роки тому
Website : www.vlsi-backend-adventure.com/routing.html TOPICS -Importance of Routing as technology shrinks. -Routing objective -Routing Definition -Inputs of Routing -Routing Constraints -Routing Flow -Global Routing -Track Assignment -Detail/Nano Routing -Detail/Nano Routing: Incremental Fixing -Search and Repair -Routing Preferences -Routing Optimization -Outputs of Routing
VLSI Physical Design: Clock Tree Synthesis (CTS)
Переглядів 20 тис.4 роки тому
website: www.vlsi-backend-adventure.com/cts.html clock tree synthesis -Difference between HFNS and CTS -Why buffer/inverters are inserted? -Difference between clock buffer and normal buffer -Inputs of clock tree synthesis (CTS) -Sanity checks before CTS -Goals of CTS -Clock latency -The clock problem -Main concerns for clock design: skew, power, noise, delay -Clock skew: positive skew, negative...
VLSI Physical Design: How to fix congestion.
Переглядів 10 тис.4 роки тому
Website: www.vlsi-backend-adventure.com Congestion If the number of routing tracks available for routing in one particular area is less than the required routing tracks then the area said to be congested.
VLSI Physical Design: Placement
Переглядів 10 тис.4 роки тому
Website: www.vlsi-backend-adventure.com/placement.html -Placement -Goals of placement -things to be checked before placement -placement flow -inputs given to placement tool -Pre-placement -Course placement, Legalization, Detailed Placement, congestion driven placement, timing driven placement. -Timing and congestion optimization -techniques for optimization. -Tasks in placement: High fanout net...
VLSI Physical Design: Powerplan
Переглядів 21 тис.4 роки тому
Website: www.vlsi-backend-adventure.com/powerplan.html Power plan Power planning is done to provide uniform supply voltages to all cells in the design. The primary objective of power planning is to ensure that all on chip components (blocks, memory, I/O cells etc...) have adequate power and ground connections. -Power Management Techniques 1. Core Power Management 2. I/O Power Management -Inputs...
VLSI Physical Design: Physical only cells
Переглядів 11 тис.4 роки тому
www.vlsi-backend-adventure.com Physical only cells End Cap Cells, Well-Tap Cells, De-Cap Cells, Filler Cells, Tie Cells & Spare Cells.
VLSI Physical Design: Floorplan
Переглядів 21 тис.4 роки тому
Website: www.vlsi-backend-adventure.com/floorplan.html First step in the Physical Design flow • Floor planning is the process of determining the Macro placement, power grid generation and I/O placement. • Floor planning involves • Defining the size of the chip or block • Pre-placing hard macros, • IO pads and other desired objects • Defining a power grid for the design. • Placing Blocks/Macros ...
VLSI Physical Design: Sanity Checks
Переглядів 5 тис.4 роки тому
www.vlsi-backend-adventure.com We need to perform some sanity checks before we start our physical design flow, to ensure that inputs received from various team such as synthesis team, library team etc are correct. If we missed this checks than it can create problem in later stage. We check mainly 3 Input files. -Library checks -Design/Netlist check -Constraint checks
VLSI Physical Design: SDC Contents
Переглядів 5 тис.4 роки тому
www.vlsi-backend-adventure.com SDC- Standard design constraints or Synopsys design constraints. -Clock definations create clock, generated clock, virtual clock, clock uncertainty, clock latency. - I/O Delays Input delay & output dalay. - DRVs Max trans, Max Cap, Max fanout. -Clock Exceptions False path, multicycle path, disable path.
VLSI Physical Design: Physical Design Inputs
Переглядів 12 тис.4 роки тому
www.vlsi-backend-adventure.com/pd_inputs.html Input Files of physical design are described in detail. Netlist(.v) Synopsys Design Constraints(.sdc) Logical Library(.lib) Physical Library(.lef) Technology File(.tf) TLU File Milkyway Library Def File
VLSI : Synthesis flow
Переглядів 17 тис.4 роки тому
www.vlsi-backend-adventure.com/logic_synthesis.html Define Synthesis Synthesis inputs outputs goals Synthesis steps Synthesis Flow HDL files and Library setup Reading files (analyze and elaborate) Design environment constraints Clock Gating Optimization constraints Compile and Compile Strategies Optimization techniques Report generation and timing analysis Write files Checklists #VLSISynthesisF...
Stroman Centers
Super Thanks a lot
Can you show how to find mcp and fp from one rtl
Why does this field always can only be taught by Indian ?
Your website is not working why
May i know what happend to the official website?
your website link is down ..please enable it.
Hello folks, your website is not working. Could you please fix it. As it will help more n more vlsi learner
The same
Why is your website not working? It used to open but now it shows error.
Hi sir Vlsi backend website is not opening from 20 days please help on this
Hello Sir , VLSI BACKEND ADVENTURE site is not working....can u please help us out - THANKYOU SIR
Website is not opening 😢
Hello sir, your website is not working,
why offcial website vlasi backend advenure is not working for lastr one week??
Website hosting plan is over and I'm working on something. It will be down for few more months
Hello sir....your site is not working since more than week days.
website is not opening... please help
Can we make changes in SDC constraints after write_sdc?
very nice , thanks alot
in which file physical cells are present
what is by 2 in chanell length
hi, can you help me. When I do the place_opt step, then I check the Global Routing Congestion, there are areas with heavy congestion. Can you tell me how to fix it?
dear sir, the topics and videos are really good. You did great work. but please don't put such music in background. it distracts more. Your voice and mild music will be the best combination. Thanks for teaching us
thankyou very very very much sir. it was a very good videos for the person who are interested in physical design . sir can you please suggest any blogs for getting more knowledge in physical design sir. please sir please help me
Hi, your website link doesn't work. Good video
Hi your website is not working please check once . Good video
your video is by far the worst. just reading the slides doesn't make a video. try to put efforts and time to read and understand the topic before you post this type of videos
i love you
hey bhai pura vlsi backend adventure se content leke yaha chipkake, tu pad raha hei. kaise hei re tu
Wo website bhi meri hi hai 🥲
@@FerozAhmed_PhysicalDesign wooowww really!!!😱 im really sorry bro, we all prefer your website only in our office, its very popular. tqsm for that content😍😍😍
@@FerozAhmed_PhysicalDesign website is down, please fix it.
Can you do video on low power design techniques,issues,and challenges in lower technology node with respect to power.
Thank you
Tq
i have recently viewed your website your really doing an amazing job. this website is clear and precise every website wouldn't be in such a way. thank you soo much!
What happen to website its not loading
One of the most detailed & clarity-driven videos I have seen. Although you can never cover everything in something as vast as PD, but still this is one the best videos series I have seen. Thank you so much
Thanks
Your website is not opening sir
Yes i know, for temp use this link www.vlsi-backend-adventure.in, will move back to .com in few days
@@FerozAhmed_PhysicalDesign ok thanks
Please try now i've fixed it
@@FerozAhmed_PhysicalDesign no sir it's not opening
Try www.vlsi-backend-adventure.com if it not opening please clear your cache memory from browser and reload it. Thanks
please help your website really helps
Thanks for the explanation! But I'm not able view the website,can you help to check it?
www.vlsi-backend-adventure.in try this, im facing some issue with commercial domain, will switch to com in few days
@@FerozAhmed_PhysicalDesign Thanks for the reply! but still can't reach the page when using .in . I will wait for the com page after the fix. Thanks！
Website is down since two days
www.vlsi-backend-adventure.in, please check now.
@@FerozAhmed_PhysicalDesign it is opened sir
the link is not opening, it is saying that the site cant be reached.
Yes i know, hosting plan is over. Need to buy domain and hosting.
Sir Can you kindly suggest a good Book for reference - Physical Design VLSI subject ??
You can find on libgen and pdfdrive.com
Very Nice Explanation With good Colorful Diagram Sir ... Thankful to you sir . The lectures and contents are really very helpful and I learned a lot from this. Thank you so much sir
Can you do powerplan using tool
Sorry mate, I don't have tool access for doing so.
@@FerozAhmed_PhysicalDesign I've tool access Can you help me in doing so
@@yeshwanthkatrapati533 no time man, working for Qcomm. Hope you know the work culture.
@@FerozAhmed_PhysicalDesign Thank You Lemme know if you're a little bit free Just I need how to do power grid after boundary cell placement
there was a typo , this is the corrected one Well Taps has nwell connected to VDD and PSUB connected to VSS
Why foundary give specific guidelines to place memories in R0 orientation
1. It depends on which tech you are working on, below 45nm orientation is requirement by foundry. Poly orientation should be same throughout the chip. So memory/macro poly orientation should match with poly orientation of the standard cell. 2. And orientation restrictions are given by keeping the target to reduce the area power and delay.
@@FerozAhmed_PhysicalDesign Thanks for the reply.. I have one more question is why we give halo to memories apart from congestion issue.
Hi, do you conduct any training course for PD?
Nope
Okkk 😷
Killed it
Excellent 👌
Excellent work and Thank you
If you are using upf and the design had 10 different power nets, then how does power rings will be created? Across each power domain you will create domain specific power ring? Also, when you have header/footer how does the power distributed to power rails?
Common power ring will be there.
Hi Sir am a m tech student will you pls provide all these PDFs i have exams from Monday plz send
I don't have pdfs for this, but you can refer to Vlsi-backend-adventure.com website for the content. Good luck for your exams.
Hi sir will you provide PDF document on your classes of VLSI plz