AXI Stream basics for beginners! A Stream FIFO example in Verilog.
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- Опубліковано 1 сер 2024
- Hi, I'm Stacey, and in this video I go over the basics of the AXI stream interface.
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0:00 Intro
0:35 Interface Overview
1:19 Ready Signal
1:57 Last Signal
2:16 Ready-Valid handshake rules
3:07 Code Explanation
5:35 Simulation Explanation
7:31 A wild bug appeared!
10:30 Full Axi
11:23 Outro
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![The AXI Protocol, AXI MM and AXI Streaming Interfaces [English]](/img/n.gif)
Hi All, Thanks for checking out my video! A couple of notes:
1) I didn't go over the KEEP and STRB signals in this video. They're basically just fancy byte-wise enables. When we get into the bigger AXI interface video I'll explain them further.
2) Code in Github here: github.com/HDLForBeginners/Examples/tree/main/UART
3) Feedback form for your comments: forms.gle/ssNwzTKiioj3RNHD9
4) Timestamps in the description if you want to find something in particular. I'll include them here below too.
Appreciate you all! Bye!!
0:00 Intro
0:35 Interface Overview
1:19 Ready Signal
1:57 Last Signal
2:16 Ready-Valid handshake rules
3:07 Code Explanation
5:35 Simulation Explanation
7:31 A wild bug appeared!
10:30 Full Axi
11:23 Outro
If one knows that the interface shall transfer fixed size packes e.g 64 words per packet, is the tlast still useful to use?
Stacey you are a gem, digital design isnt represented enough on the internet especially at this level of tutorial/instructions. Its all just opaque as hell documentation. Thank you for your service!
OMG I ABSOLUTLY appreciate how you found a bug and immediatly put up to solve it live(ish). It's so much sothing seeing experienced people having mistakes too and solve them as they go. Such a great job!
Thank you Stacey, it is a wonderful video. I look forward to more videos on AXI stream:)
Awesome content! Thanks Stacey!
Thank you.
Can't wait to get started
on my journey.
Wonderful Stacey!!
This is one of my favorite youtube channels and I don't get zoned out while learning. I am a beginner in this industry right now and your videos are so so so helpful!
Please make further parts as soon as you can!
Excellent explanation. Thanks.
Thanks so much Stacey!
Looking forward to the next one!
I asked chatGpt about good tutorials on Verilog, he recommended this Channel 😂. I love it. Keep it up 👍
excellent content very useful, thank you for posting
I'm newly hired in an FPGA company and am still learning protocols. This is an excellent introduction to something quite simple but bogged down by its documentation. Thank you!
Aaaand mine was the 255th like . . 8 bits well deserved to say the least. Thank you very helpful stuff
Awesome video!
amazing~ thanks
Thank you so much for making these amazing videos!
Would it be possible to also occasionally show a high-level block diagram of the architecture? I think it would be helpful in understanding where the different modules fit and how they connect to each other.
Looking forward to the next one!
This is a great suggestion! After I made the video I realised it probably would be beneficial, especially for anything bigger than this. Will definitely include it next time.
very nice job :) thanks
amazing
nice
Hey Stacey, thank you for the amazing video! Do you have a code where you pack/unpack data from axi bus? Also, i could not see the fifo code in github, it is some. xci file that does not show the verilog code....
really?? I think that only male work with fpga, you are great lucy! good job!
Hi Stacey, thanks for pushing good contents to UA-cam! If I understood correctly, around 9:40 you mentioned about a time out for "not driving ready" and said that slave must become ready at some point. Actually, I have never heard about a limit on ready, AFAIK the slave can keep ready indefinitely. I did a quick check on AXI Reference Guide from Xilinx and other resources and didn't find an information about a time out value. Do you have a reference for this or did I understand it wrong? Thank you!
Hi, thanks for your comment! You're absolutely correct. That was the point I was trying to make at 9:42, there isn't a time specified! :)
@@FPGAsforBeginners Sorry, my mistake. I listened again and you said there isn't a specified time but what I heard was "there is". Thanks for the response :)
Hi, just curious which EDA/platform you are using for writing SV and generating waveform?
I used Vivado for this :)
Hi! If i build custom IP, with signals bus compatible to full AXI4, and connect it to Zynq for example in Vivado, how can I configure the setting so I can use it in burst mode?
Hello Stacey . Interested in MIPI CSI-2 before?
Hi Stacey, Thank you for you video! Can you please show how you made/generated(what parameters you selected when generating the XCI) AXI tx_fifo to stream data to UART? Not sure if you already have a video on this. It'd be a great help if you can do this please. Thanks! :)
I did make a video! Here ya go! ua-cam.com/video/9f4i1Fq7xak/v-deo.html
@@FPGAsforBeginners Thank you Stacey! I also filled out the google form and requested some video on JESD204B related topic. Any help would be appreciated!
Why there's no "read response" signal?
This is AXI-Stream, which doesn't have a read response. The AXI and AXI-Lite interfaces use that signal.
@@FPGAsforBeginners Got it! thanks!
Where is the freaking fifo code? lol
Hi. tank u for you describing about some subject that is so rare to read, but can u please wear a normal make up . and again thanks for all your work u have done.
Hello Stacey . Interested in MIPI CSI-2 before?