Відео

Very nice! You can also see the RTL schematic in Vivado

Thankyou

thanks!

You might be surprised how few tutorials on youtube cover this level of detail; excellent job you've answered many questions for me!

Hi Stacey. I see you are using System Verilog here. Do you still use old-school verilog too? If so, when?

Orn Camp

Hello! Thanks for the video! Wouldn't be interested to do a video about ADC, FMC and how to use them? Thanks!

Thank you Stacey! great video and I love the cliff cummings paper, sunburst papers for FIFO design and CDC are good too......😁

I have wanted to do an FPGA project for quite awhile now and haven´t gotten around to it. I wanted to create maybe a small 8-bit microcontroller with the alu and a large enough instruction set to be considered general purpose, with registers, and control, etc. There are several companies that offer fpga development boards, could you recommend one to me that would be sufficient to complete my goals? I would like to code in Verilog preferably but VHDL would be fine also.

This video was so freaking good it was so clear and to the point thanks for this

Could be combined into one synchronous always block, don’t need three blocks.

My favorite statemachine is synchronous and not pseudo synchronous like your statemachine. The synthesized result is mostly the same, but one extra clock cycle per state. It’s my preferred method.

Thanks for showing this webpage, and that you provided an actual link to it. It was very easy to get started and get hands on.

Great tutorial😊 does state_counter consume more energy because of state transitions (for counter value itself) for states that don't use it?

I'm so happy to have found this channel! Thanks for your content!

LFSRs are very interesting structures with many uses. Eg. GPS codes.

Almost 10k subs. Catching fire!

Everyone should have a favorite state machine! Thanks Stacey, educational as always.

Amazing work as usual, thank u for the great effort 😊

As a colleague engineer I love your content

Hi Everyone and thanks for checking out my new video! I'm really happy with this one! Phew! It has taken a month of prep and 3 recording attempts to get it exactly as I like it, but now I can happily say I've distilled my favourite state machine (and surrounding topics) into 30 min! Hope you enjoy!

amazing videos

Thank you for your job ❤

Hi, I am having a problem while creating application project. I have followed both the parts carefully, but when creating a project on Vitis IDE, while selecting a template at 4:20 both the next and finish buttons are disabled except for the blank C and empty C++ project, and by doing so I do not have platform and configs libraries and headers

Hi, Stacey! I just finished trying this in Vivado + Vitas v 2024.1.1 and it seems that the two sides of the BRAM are not connecting to each other. Any ideas of how to debug it? Thanks!

These three Zynq series are quite useful but they are good only for people who already have some experience with the device and the tool not for the beginners. It is also presented too fast. Please go slower in your next videos and present it with more explanations. Also having your face video is distracting especially when you have to move it from right to left and left to right, either omit it or make it much smaller. I think adding an XADC block to your design for the next video clip would be a very helpful topic. Overall, a great work!

Hi Stacey! you have been doing a great job on fpga explanation, could you please make some video to explain how KEEP and DON'T TOUCH keywords working in vivado. I barely can't find a good explanation on internet. thanks

I would like to ask a question that make me confused regarding big or little endian you mentioned. Lets assume that the package to be transmitted to the interface PHY has a number of bits in a sequence p0, p1, p2, p3...pN. How should I transmit them using MII interface format: p0->tx[0], p1->tx[1], p2->tx[2], p3->tx[3] in one clock or pN-3->tx[0], pN-2->tx[1], pN-1->tx[2], pN->tx[3] in one clock? Thank you.

Thank you for the video! Very helpful!

Maam, please add more videos , love your methods and way of explanation. Thank You

what is the idea of using numpy.arange(1000) instead of just using range(1000) ? i've never seen that before, the execution time if 2 times slower and the space complexity is O(N) compared to range which is O(1) because it's just a generator.

Nice explanation.

Dear teacher I have built a module using PL part only to calculate the summation of Bytes. Now, I try to use the Zynq with axi-gpio to read the final value of the summation. I test each circuit individually, it is works correctly. The problem is that when I connected them together (the PL with PS), I did not get any results by the Zynq at the serial monitor. Please, if you can help. Thanks.

please keep up the good work, i just stumbled on your AXI explanat ion video and it taught me more then a year long vhdl mentor at my company (he had a lot of knowledge, but was a bad teacher)

Thank you, Stacey! Great job helping the folks like me that are new to FPGA!

Excellent! Thank you, Stacey, great job. You're explanation of the processing of the 'how' and 'why' are super!

this video helped me quite a lot. Thx!

Dear teacher Please, I have a problem during reading the status of an output switch on Zybo Z7-10. I use Vitis to program the Zynq processor with Gpio connected to a slid switch. I make the switch (input2) status as a condition as shown in the program below if (D == 1) ; The following program works only when the input2 signal that was connected to Gpio IP starts from ("1") but the program does not work when input2 signal starts from ("0"). ////////// while (1) { D = XGpio_DiscreteRead(&input2, 1); // input2 from a slide switch if (D == 1) { sum_all = XGpio_DiscreteRead(&input, 1); // input is a 32-bit data printf("%x " , sum_all); sleep (1); } else { XGpio_DiscreteWrite(&output, 1, 0); // output is a LED printf("No_Signal "); sleep (1); } } ///////////// i.e. the program works only when I change input2 from "1" to "0" but does not work when the input2 start changes from "0" to "1".

Excellent video as always! I would love it if you could show how to do a FIR filter, showing multiplication/accumulating and rounding, and pointer handling, without timing errors! Thanks so much 🙂

Why do you need to use create_clock constraint? What does this actually create? The top module has name clk. But what does sysclk do? Isn't it sufficient to mention the Pin and IO std.

thank you for the amazing explanation:) love the enthusiasm

Thanks a lot from Italy

amazing ✨✨

Hi, I’ve been following your videos, and they are really good. I wanted to ask for a favor, if you don’t mind. Could you please make another video on STA with a real-time example, such as a FIFO or some protocols? In that video, it would be great if you could explain how to solve timing issues like negative slack, setup, and hold time violations.

Could you please make a tutorial on how to re-upload a .mem file after making changes to it so that we don’t need to re-generate a bitstream? Many thanks!