Timing Constraints: How do I connect my top level source signals to pins on my FPGA?

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  • Опубліковано 24 гру 2024

КОМЕНТАРІ • 36

  • @near--zero
    @near--zero 2 місяці тому +1

    You might be surprised how few tutorials on youtube cover this level of detail; excellent job you've answered many questions for me!

  • @AlirezaSohrabi-vq1bm
    @AlirezaSohrabi-vq1bm Рік тому +2

    You're a legend in teaching!

  • @emiliomartineziii2980
    @emiliomartineziii2980 4 місяці тому +1

    Is there a video showing how to use a pmod pin as an external clock? Sometimes I think I works for some pins and not for others and I dont completely understand why

  • @imagiro1
    @imagiro1 Місяць тому

    Well, look at that! Finally some useful tutorial that actually answers some of my questions! :)

  • @prydin
    @prydin 9 місяців тому +1

    Thank you! Thank you! Thank you! I've been wading through horrible attempts at explaining this (including things from AMD themselves) to no avail. Your explanation is crystal clear!

  • @bretfuzz925
    @bretfuzz925 7 місяців тому

    I got finished with a fairly complex design. I feel like I have missed a lot of the fundamentals even though the design is sound. I am grateful I have found your channel to help me take a step back and gain more strength in the foundation. Thanks!

  • @berkankorkmaz1923
    @berkankorkmaz1923 3 роки тому

    That video is like god gift for me. I was looking for how to generate constraints file everywhere and can't find. I wanna thank you with all my heart.

  • @aaronlinell3916
    @aaronlinell3916 2 роки тому +3

    Wonderful. This is an oft overlooked aspect of programmable logic.

  • @marwanal-yoonus280
    @marwanal-yoonus280 2 роки тому +1

    Thank you for the helpful illustration.

  • @JohnScott-t1y
    @JohnScott-t1y Рік тому

    Thanks so much for this clear explanation. So many tutorials overlook this very basic information!

  • @dhaneshprabhu72
    @dhaneshprabhu72 2 роки тому +1

    Great vdo. This has helped me to kickstart my 'code on board' journey

  • @MegaCarbonMonoxide
    @MegaCarbonMonoxide 3 роки тому +2

    Great video for FPGA beginners like me. Thank you.

  • @mikhailchesnokov2966
    @mikhailchesnokov2966 10 місяців тому +1

    Thank you! You are the best teacher!!!

  • @VigneshD25
    @VigneshD25 3 роки тому +1

    Hi,
    If the clock is driven by Crystal, what exactly does create_clock constrain does ? Thanks

    • @FPGAsforBeginners
      @FPGAsforBeginners  3 роки тому +4

      It tells the FPGA what the crystal frequency is. create_clock doesn't *make* the clock, it just tells the tool the clock exists.

  • @mrshodz
    @mrshodz 2 місяці тому

    Nice explanation.

  • @vyphan-q2c
    @vyphan-q2c 5 місяців тому

    What type of board do you use with the Artix-7

  • @bennguyen1313
    @bennguyen1313 2 роки тому

    I understand specifying which pin is the clock, and mapping a net-name to a pin.. but how do you constrain a design such that it performs appropriately? For example, when interfacing to some high speed external memory device, or using logic to measure the pulse width of an incoming signal?

  • @abhishek1831994
    @abhishek1831994 3 місяці тому

    Why do you need to use create_clock constraint? What does this actually create?
    The top module has name clk. But what does sysclk do?
    Isn't it sufficient to mention the Pin and IO std.

  • @ABABA30175
    @ABABA30175 2 роки тому

    Thank you for your tutorial, help me to learn how to add and write the xdc file.

  • @dimitrioskechagias2088
    @dimitrioskechagias2088 3 роки тому +1

    Thank god I found this video.

  • @blueeengineer4373
    @blueeengineer4373 3 роки тому +1

    How do you find the proper iostandard ?

    • @FPGAsforBeginners
      @FPGAsforBeginners  3 роки тому +1

      The documentation should say, if it doesn't you need to look at the schematic, or ask the company who made the board. Usually the schematic contains different voltage supplies or regions, and those should be labelled. LVCMOS33 for 3.3V supplies, etc. it's more complicated (eg LVDS) than that so usually if you don't know, or want to double check, ask the company/board designer.

    • @blueeengineer4373
      @blueeengineer4373 3 роки тому

      @@FPGAsforBeginners assume that board designer routed the lines to a connector on the board and you can tie variety of interfaces to the pins in this case through connector. Does still board owner can provide me iostandard or is it my responsibility to find out?

    • @FPGAsforBeginners
      @FPGAsforBeginners  3 роки тому +1

      @@blueeengineer4373 It depends. Some FPGAs have IO banks where an entire group of IOs will use the same power supply. So even if some of those IO pins are routed off board, you can look at the power supply of the bank and infer it that way. So even if it's connected to a connector, the bank it's using should have a supply. But knowing what it is connecting to is a good idea anyway, because in some cases (eg digilent pmod) pins can be either an input or an output depending on what's connected. So ultimately the board designer should be able to give you an IO Standard even if some of the pins are routed off-board. But the directions may depend on what's connected.

  • @xenofonsiafakas1759
    @xenofonsiafakas1759 3 роки тому +6

    With this video you learn more stuff than you would with 100 xilinx videos ...

  • @gyaneshwar345
    @gyaneshwar345 3 роки тому

    Very useful and much needed ... thanks

  • @vladislavbutkobvo1209
    @vladislavbutkobvo1209 6 місяців тому +1

    Thanks for video, maybe it push me forward

  • @ΝικΝοκ
    @ΝικΝοκ 2 роки тому

    hi , very nice video !! could it be possible that you do something similar with sipeed board (tang primer 20k). I guess the constraint files are not all the same . thanksss!!!!

  • @АндрейК-ж3к6ю
    @АндрейК-ж3к6ю Рік тому

    Thanks Stacey for this video. Hello from Ukraine ;)

  • @karolus8517
    @karolus8517 2 роки тому

    Hi Stacey. What does sysclk refer to? Is it an alias used within more complicated constraint files? Thank you so much for this video series!

    • @BlackBot1986
      @BlackBot1986 2 роки тому

      i'm not using the same software but i would guess that is the name which this clock is refered in the timing analysis... just a guess.

  • @thegent5167
    @thegent5167 3 роки тому

    Thank you very much for this great content

  • @raulvalenciavasquez
    @raulvalenciavasquez 11 місяців тому +1

    +1
    Thx for your videos

  • @abhisheksrivastava7134
    @abhisheksrivastava7134 3 роки тому

    Thank a lot.

  • @lowmax4431
    @lowmax4431 3 роки тому

    Damn I wish they taught me this in school.