Is there a video showing how to use a pmod pin as an external clock? Sometimes I think I works for some pins and not for others and I dont completely understand why
Thank you! Thank you! Thank you! I've been wading through horrible attempts at explaining this (including things from AMD themselves) to no avail. Your explanation is crystal clear!
I got finished with a fairly complex design. I feel like I have missed a lot of the fundamentals even though the design is sound. I am grateful I have found your channel to help me take a step back and gain more strength in the foundation. Thanks!
I understand specifying which pin is the clock, and mapping a net-name to a pin.. but how do you constrain a design such that it performs appropriately? For example, when interfacing to some high speed external memory device, or using logic to measure the pulse width of an incoming signal?
Why do you need to use create_clock constraint? What does this actually create? The top module has name clk. But what does sysclk do? Isn't it sufficient to mention the Pin and IO std.
The documentation should say, if it doesn't you need to look at the schematic, or ask the company who made the board. Usually the schematic contains different voltage supplies or regions, and those should be labelled. LVCMOS33 for 3.3V supplies, etc. it's more complicated (eg LVDS) than that so usually if you don't know, or want to double check, ask the company/board designer.
@@FPGAsforBeginners assume that board designer routed the lines to a connector on the board and you can tie variety of interfaces to the pins in this case through connector. Does still board owner can provide me iostandard or is it my responsibility to find out?
@@blueeengineer4373 It depends. Some FPGAs have IO banks where an entire group of IOs will use the same power supply. So even if some of those IO pins are routed off board, you can look at the power supply of the bank and infer it that way. So even if it's connected to a connector, the bank it's using should have a supply. But knowing what it is connecting to is a good idea anyway, because in some cases (eg digilent pmod) pins can be either an input or an output depending on what's connected. So ultimately the board designer should be able to give you an IO Standard even if some of the pins are routed off-board. But the directions may depend on what's connected.
hi , very nice video !! could it be possible that you do something similar with sipeed board (tang primer 20k). I guess the constraint files are not all the same . thanksss!!!!
You might be surprised how few tutorials on youtube cover this level of detail; excellent job you've answered many questions for me!
You're a legend in teaching!
Is there a video showing how to use a pmod pin as an external clock? Sometimes I think I works for some pins and not for others and I dont completely understand why
Well, look at that! Finally some useful tutorial that actually answers some of my questions! :)
Thank you! Thank you! Thank you! I've been wading through horrible attempts at explaining this (including things from AMD themselves) to no avail. Your explanation is crystal clear!
I got finished with a fairly complex design. I feel like I have missed a lot of the fundamentals even though the design is sound. I am grateful I have found your channel to help me take a step back and gain more strength in the foundation. Thanks!
That video is like god gift for me. I was looking for how to generate constraints file everywhere and can't find. I wanna thank you with all my heart.
Wonderful. This is an oft overlooked aspect of programmable logic.
Thank you for the helpful illustration.
Thanks so much for this clear explanation. So many tutorials overlook this very basic information!
Great vdo. This has helped me to kickstart my 'code on board' journey
Great video for FPGA beginners like me. Thank you.
Thank you! You are the best teacher!!!
Hi,
If the clock is driven by Crystal, what exactly does create_clock constrain does ? Thanks
It tells the FPGA what the crystal frequency is. create_clock doesn't *make* the clock, it just tells the tool the clock exists.
Nice explanation.
What type of board do you use with the Artix-7
I understand specifying which pin is the clock, and mapping a net-name to a pin.. but how do you constrain a design such that it performs appropriately? For example, when interfacing to some high speed external memory device, or using logic to measure the pulse width of an incoming signal?
Why do you need to use create_clock constraint? What does this actually create?
The top module has name clk. But what does sysclk do?
Isn't it sufficient to mention the Pin and IO std.
Thank you for your tutorial, help me to learn how to add and write the xdc file.
Thank god I found this video.
How do you find the proper iostandard ?
The documentation should say, if it doesn't you need to look at the schematic, or ask the company who made the board. Usually the schematic contains different voltage supplies or regions, and those should be labelled. LVCMOS33 for 3.3V supplies, etc. it's more complicated (eg LVDS) than that so usually if you don't know, or want to double check, ask the company/board designer.
@@FPGAsforBeginners assume that board designer routed the lines to a connector on the board and you can tie variety of interfaces to the pins in this case through connector. Does still board owner can provide me iostandard or is it my responsibility to find out?
@@blueeengineer4373 It depends. Some FPGAs have IO banks where an entire group of IOs will use the same power supply. So even if some of those IO pins are routed off board, you can look at the power supply of the bank and infer it that way. So even if it's connected to a connector, the bank it's using should have a supply. But knowing what it is connecting to is a good idea anyway, because in some cases (eg digilent pmod) pins can be either an input or an output depending on what's connected. So ultimately the board designer should be able to give you an IO Standard even if some of the pins are routed off-board. But the directions may depend on what's connected.
With this video you learn more stuff than you would with 100 xilinx videos ...
Very useful and much needed ... thanks
Thanks for video, maybe it push me forward
hi , very nice video !! could it be possible that you do something similar with sipeed board (tang primer 20k). I guess the constraint files are not all the same . thanksss!!!!
Thanks Stacey for this video. Hello from Ukraine ;)
Hi Stacey. What does sysclk refer to? Is it an alias used within more complicated constraint files? Thank you so much for this video series!
i'm not using the same software but i would guess that is the name which this clock is refered in the timing analysis... just a guess.
Thank you very much for this great content
+1
Thx for your videos
Thank a lot.
Damn I wish they taught me this in school.