Multiplier IP Block Design Verification in Vivado.

In this video, a multiplier IP block design was created. Then it was converted to Verilog model for verification. Then verification is performed without writing a testbench in Xilinx Vivado.

[@TejasBhaskarJagtap-ex3wo]

Thank you so much sir 👍

[@dr.hariprasadnaikbhattu]

You are Welcome

[@nassalma8007]

@@dr.hariprasadnaikbhattu can you help me please for something

[@nassalma8007]

hello

[@dr.hariprasadnaikbhattu]

Hi, what do you want to ask.

[@nassalma8007]

plese i need your help to run my code@@dr.hariprasadnaikbhattu

[@rsn8515]

Error Elaborate steps failed.. How to rectify

[@dr.hariprasadnaikbhattu]

Have you created the HDL Wrapper step before simulation

[@rsn8515]

@@dr.hariprasadnaikbhattu yes.. Error is multiplier module not found

[@animal.lover3463]

Nice

[@dr.hariprasadnaikbhattu]

Welcome

[@shilpakesav]

Hi sir how can i contact you?

[@dr.hariprasadnaikbhattu]

Hi, what is the need. Any doubt