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Dr.HariPrasad Naik Bhattu
India
Приєднався 25 сер 2012
Welcome to Dr.HariPrasad Naik Bhattu's UA-cam Channel!
Are you aspiring to excel in the world of VLSI? You've found the perfect resource! This channel is dedicated to providing practical, industry-oriented exposure on VLSI CAD tools.
My primary objective is to assist VLSI students and engineers with their project work, offering valuable insights and hands-on guidance. Subscribe and stay tuned for expert tutorials, project walkthroughs, and all the support you need to succeed in your VLSI endeavors.
Let's make your learning journey both enlightening and enjoyable! 🚀
Are you aspiring to excel in the world of VLSI? You've found the perfect resource! This channel is dedicated to providing practical, industry-oriented exposure on VLSI CAD tools.
My primary objective is to assist VLSI students and engineers with their project work, offering valuable insights and hands-on guidance. Subscribe and stay tuned for expert tutorials, project walkthroughs, and all the support you need to succeed in your VLSI endeavors.
Let's make your learning journey both enlightening and enjoyable! 🚀
HYBRID FULL ADDER in Cadence | Delay | AvgPower | PDP.
HYBRID FULL ADDER in Cadence | Delay | AvgPower | PDP.
Переглядів: 412
Відео
2-BIT Binary MULTIPLIER Design using Half Adders | Cadence.
Переглядів 448Місяць тому
This video shows the design and implementation of 2-BIT Binary MULTIPLIER using Half Adders in Cadence Virtuoso.
Digital COMPARATOR (1-Bit) Design in Cadence.
Переглядів 356Місяць тому
This video shows the implementation of a 1-Bit digital comparator design in Cadence Virtuoso. It compares A and B bits and yields A less B, A=B and A greater B.
Calculate the CLOCK FREQUENCY of TSPC D-Flip Flop.
Переглядів 381Місяць тому
This video shows how to calculate the clock and output frequency of a TSPC D-Flip Flop in Cadence Virtuoso.
TSPC D-Flip Flop Design in Cadence Virtuoso.
Переглядів 1,3 тис.Місяць тому
This video show the design of Edge Triggered True Single Phase Clock (TSPC) D-Flip flop in Cadence Virtuoso.
SCHMITT TRIGGER in Cadence Virtuoso.
Переглядів 375Місяць тому
This video explains about the design of a Schmitt Trigger Circuit in Cadence Virtuoso. Schmitt Trigger is a Sine wave to a Square Wave converter.
PVT Analysis of CNTFET STI Inverter in Cadence.
Переглядів 4513 місяці тому
This video describes about the process, temperature and voltage variation of a 32nm CNTFET Standard Ternary Inverter design in Cadence Virtuoso.
Subthreshold CN-FET Inverter Avg Power & Delay in Cadence.
Переглядів 3073 місяці тому
This video explains about the design and analysis of a Carbon Nano FET Inverter in Subthreshold region for Low Power applications in Cadence Virtuoso. Average Power and Delay analysis is also illustrated.
TERNARY NAND with AVG Power and Delay in Cadence.
Переглядів 3343 місяці тому
This video explains the design and implementation of a multi-valued Ternary NAND gate using CNTFET in Cadence Virtuoso.
Ternary STI, PTI & NTI Design Using CNTFET in Cadence.
Переглядів 2823 місяці тому
This video explains the design and analysis of a Multi-valued logic such as the STI, PTI and NTI Inverters using Carbon Nano Field Effect Transistors in Cadence ADE Assembler.
Multi-Valued (Ternary) Logic of STI in Cadence Virtuoso.
Переглядів 2493 місяці тому
This video is about the design and analysis of Multi-Valued (Ternary) Logic (0,1,2) Standard Ternary Inverter using 32nm Carbon-Nano FET in Cadence Virtuoso ADE Assembler.
CNFET Standard Ternary Inverter (STI) in Cadence Virtuoso.
Переглядів 4093 місяці тому
This video explains about the implementation and analysis of a Multi-Valued Standard Ternary Inverter (STI) with Carbon-Nano FET using Cadence Virtuoso.
Configurable Parameter used CHANGE Width in Counter IP.
Переглядів 1854 місяці тому
This video is all about the use of a configurable parameter for changing the counter WIDTH to different bits in an IP using Xilinx Vivado.
8-BIT UP/DOWN COUNTER IMPLEMENTATION in VIVADO.
Переглядів 6444 місяці тому
This video shows the implementation of a 8-Bit Counter using Verilog HDL in Xilinx Vivado.
Full Adder Implementation using Half Adder IP.
Переглядів 2694 місяці тому
This video explain the process of implementing a Full Adder design using two Half Adder IP's using Verilog HDL in Xilinx Vivado.
Low Noise Amplifier Transient and DC Analysis.
Переглядів 3444 місяці тому
Low Noise Amplifier Transient and DC Analysis.
REAL PARAMETER TUNING of CS Amplifier in Cadence Virtuoso.
Переглядів 4774 місяці тому
REAL PARAMETER TUNING of CS Amplifier in Cadence Virtuoso.
DC, SP, Transient Analysis of LNA in ADE Assembler.
Переглядів 4784 місяці тому
DC, SP, Transient Analysis of LNA in ADE Assembler.
CMOS Low Noise Amplifier Analysis using S-Parameter.
Переглядів 6204 місяці тому
CMOS Low Noise Amplifier Analysis using S-Parameter.
S-Parameter Analysis of Cascode Common Source Amplifier.
Переглядів 2774 місяці тому
S-Parameter Analysis of Cascode Common Source Amplifier.
Cascode Common Source Amplifier Analysis in Cadence.
Переглядів 1,5 тис.4 місяці тому
Cascode Common Source Amplifier Analysis in Cadence.
Parametric Sweep of a CS Amplifier in Cadence Virtuoso.
Переглядів 4994 місяці тому
Parametric Sweep of a CS Amplifier in Cadence Virtuoso.
Common Source Amplifier Configuration in Cadence Virtuoso.
Переглядів 2,3 тис.5 місяців тому
Common Source Amplifier Configuration in Cadence Virtuoso.
6T SRAM Process Corner Analysis in ADE Assembler.
Переглядів 7485 місяців тому
6T SRAM Process Corner Analysis in ADE Assembler.
CORNER ANALYSIS OF 6T SRAM IN CADENCE.
Переглядів 1,4 тис.5 місяців тому
CORNER ANALYSIS OF 6T SRAM IN CADENCE.
6T SRAM DC Analysis in Cadence Virtuoso.
Переглядів 4,4 тис.5 місяців тому
6T SRAM DC Analysis in Cadence Virtuoso.
Binary Counter IP with Threshold, Reset in Vivado.
Переглядів 3355 місяців тому
Binary Counter IP with Threshold, Reset in Vivado.
UP/DOWN Binary Counter IP in Vivado.
Переглядів 4075 місяців тому
UP/DOWN Binary Counter IP in Vivado.
Utility Vector & Utility Reduced Logic in Xilinx Vivado.
Переглядів 2385 місяців тому
Utility Vector & Utility Reduced Logic in Xilinx Vivado.
thank you very much I' m finished design this anternna.
thanks a lot Sir❤❤😮😅 sir plx give me schematic of 3 input xor gate and truth table schematics for verification of truth table can you email it to my email id plx sir 😢😢i cannot find anywhere in internet iam your new subscriber 😊😊
Sir, I am learning the basics. I don't find Cmos in the circuit. Can't understand why we call it Cmos LNA. Could you please explain?
Sir, i am getting the delay plot instead of the value what parameters I have to change to get the delay value
Sir which software is this?
Hi, this software is called as Electric VLSI Design System
Thank you sir
Welcome
Sir, thank you for the reply
Thanks and Welcome.
how to find the threshold of the CNTFET bu changing the diameter in the tool
Hi, check this video. At time 0:41 you can change the parameters of CNTFET and at time 1:04 threshold voltage plot. ua-cam.com/video/fGaadUGC2Es/v-deo.html
Hello, I made a 6 -BIT binary multiplier in cadence and when I make a change for all inputs to go form 0 to 1 and plot the current through my voltage source (At VDD = 1.2 V), it appears that the current ripples between -5 and 5 Amps which is very surprising to me. Do you have any suggestions? Thank you!
Hi, are you plotting the current or voltage. Are you providing the constant source such as Vdc or Vpulse.
Help me with how to make the partial ground for microstip rectangular antenna. It's part of my major project.
Hi, Not in Antennas now.
Sir please provide the download link of model file
Hi, I have attached the files that I have. Below the video links are attached ua-cam.com/video/qhsleQAAj3g/v-deo.html
graph is like noise signal
Hi, check you have provided the Vdc and gnd. Also check the voltages of pulse source where you gave V V twice while declaring the V1 and V2.
Sir even after attaching the mode files I'm facing an issue in the simulation of ADE Assembler. Does the assembler works in the cracked version of Cadence
Yes, it works. What is the check it in Google once.
I am unable to see my Assura button in layout view . Although I do have files for ASSURA41 . Can someone help ?
Hi, check you have Assura or Calibre for DRC and LVS
I am unable to see my Assura button in layout view . Although I do have files for ASSURA41 . Can someone help ?
Hi, you might have Calibre instead of Assura. Check once again.
Sir, I tried the same but the delay is negative
Hi, be specific about the time where you got negative.
Sir, how can we apply such optimization for CNTFET, I tried but I am not able to view the parameters
Hi, watch the below video from 7:58 on wards or watch full video ua-cam.com/video/EvB6xWwwrt8/v-deo.html
Sir, in this design ur using Zigzig(m,0) kind of CNTFET why not the other type
Hi, mention the video time so that it is easy to locate.
how to get the 14nm technology of CMOS, can you share the link of PTM library files
Hi, I have attached the files that I have. Below the video links are attached ua-cam.com/video/i5FY7XLmKeA/v-deo.html
Sir can you share the PTM model library files of 14nm, 16nm and 22nm
Hi, I have attached the files that I have. Below the video links are attached ua-cam.com/video/i5FY7XLmKeA/v-deo.html
Sir, may i Know how to do parametric analysis for gain or AR plot
Hi, for parametric analysis use this video ua-cam.com/video/iKXujuS7OfI/v-deo.html
Super sir Thank you sir
Welcome
Thank you so much sir its really helpful now im free of doubts ☺️
Thanks and Welcome for your response
if I am designing a 3 inputs nor, do I do the same process for Vss and Vdd?
Hi, vdd and vss remain same only the topology of transistor changes
Thank you so much!
Thanks and Welcome
Dear sir, In av Extracted view only resistors are visible capacitors are not visible.!!!!!!!!!!!!
Hi, capacitors are present between two metal layers. Zoom it and see
@dr.hariprasadnaikbhattu yes sir got it
sir i tried but in the end its showing "spectre terminated prematurely due to fatal error." what's the solution
Hi, check for the error in the log Window and resolve
Thank you sir
Sir your videos have been very useful! Could you please sir make video with Vitis or HLS and adding blocks from HLS into Vivado sir. Thank you.
Hi, I will try to do it
I was using Vivado 2018.3 version and as you know when we open it on home screen there comes recent project on right side. by mistakely I closed it and now I want it back again so how to bring it back, kindly help or tell me the steps, please
Hi, open the Vivado Then go to Tools tab at top Tool Setting ---Project Default Project Directory Enable --- Last project directory
can you design a whip antenna for low frequencies ??
Hi, I am not in to antenna now
@@dr.hariprasadnaikbhattu ok thanks
Sir I am getting distorted output how to solve it
Hi, check you have provided input and vdd properly.
Sir, looking forward to you video on CML multiplexer
I will need some time
I will need some time
Can we calculate upper thershold voltage and lower threshold voltage ? Sir can you make video on this please
Hi, are you asking about Hysterisis loop
@dr.hariprasadnaikbhattu yes sir
Sir I connected board even after implementation, I did not get the VIO and ILA are appeared after bumping the design in the board.
Hi, have you assigned the pin of the FPGA boards
Sir I followed all the steps correctly but my graph not make butterfly.Please help sir
Hi, just go through the process once again. I don't know where you are struck
Thank you!
Thanks and Welcome for the response
I am working with ZCU7104 board i followed the same procedure, bitstream is generated but after implementation ILA and VIO did not appear.
Hi, once bitstream is generated. Have you connected the board for programming or not
Sir can we follow the same procedure to implement the same design in different FPGA
Hi, process for any board is same.
Sir can you please provide me a research paper of this video cause I need for my college project and it's very urgent
Hi, I don't have any research paper. It was done as apart of online course. But you can search on internet regarding the Microstrip Patch design.
Like!
Thanks and Welcome
Very nice explanation! Thanks a lot!
Thanks and Welcome
Hi sir, is it possible you can show us how to design cmos AND-OR-inverter + OR-AND-inverter as well. and 2:1 mux with cmos as well. thank you
Hi, do you mean in LtSpice or any other tool
Very useful thankyou ❤
Thanks and Welcome
sir ,how can we install finfet libraries ?please explain
Hi, FinFet Libraries should be available with Cadence tools. Finfet transistor models must be supported by the tool.
Is 14nm technology is available of finfet? Sir
sir can you explain finfet technology
Hi, I think I have answered your question.
how we will get 180nm library file
Hi, Try this link, It has 130nm, 180nm drive.google.com/file/d/1WdWIs12BQCoKYMo0WV7o3dUoFsi-XGsh/view
good explaination sir
Thanks and Welcome
jeeooo ustaad taaanuuu looooveee
Thanks and Welcome
Good explanation sir thank you very much.
Thanks and Welcome for the response.
The parametric simulation under tool tab is not there, what to do sir ?
Hi, It should be under Tool Tab only. I searched all through the tool. I could not find else where. Are you using ADE-L or ADE-XL