Vivado Tutorial: Turn Verilog IP into AXI Module

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  • Опубліковано 24 гру 2024

КОМЕНТАРІ • 10

  • @stevenalexander6262
    @stevenalexander6262 4 місяці тому

    very nice, AXI is so new to me and I just wanted to use my newly made verilog code on my pynq, this helped tons

  • @mriosrivas
    @mriosrivas 3 роки тому +1

    This is what I was looking for. Thank you so much, I really appreciate your effort!

  • @weiyizhang4317
    @weiyizhang4317 3 роки тому +1

    Hello, thank you for the lesson very much! I wonder is there any example which uses both input and output axi stream? Thanks a lot!

  • @susmitamaloji7111
    @susmitamaloji7111 Місяць тому

    How to create that twophase program in this video. If anyone know plz reply to this

  • @MonishaK-sh9bk
    @MonishaK-sh9bk 8 місяців тому

    i want to know how to give my data into the IP, using SDK , please provide any video or documents

  • @beccadls2838
    @beccadls2838 4 роки тому

    Didn’t understand a word of this but cool!

  • @kirtikumarbaba
    @kirtikumarbaba 4 роки тому

    it's useful thanks.!

  • @iremnurcolak620
    @iremnurcolak620 3 роки тому

    Hello, what is IP? I was looking for AXI implementation but I came across IP in UA-cam a lot. I do not know what it is actually. Thanks :)

    • @clintlemire8741
      @clintlemire8741 11 місяців тому

      Intellectual Property. In this context, it is referring to your design.