Signal Ground Power Ground 4-Layer Stackup? PCB Design Explained!
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- Опубліковано 19 тра 2024
- Tech Consultant Zach Peterson focuses on a kind of stackup making the rounds on social media lately: Signal Ground Power Ground. This method has been gaining popularity among electronics designers for its ability to enhance the performance and reliability of 4-layer PCBs. But should you use it?
Zach unravels the mysteries behind these stackups, shares his expert insights, and showcases design examples to guide you on how to utilize this stackup method effectively.
0:00 Intro
0:37 Power & Layer 3
3:32 Breaking Down the Stackup
7:43 Candidates for this Stackup
👉 SIG/GND/SIG + PWR/GND Stackups: Will This Work in 4-Layer PCBs: resources.altium.com/p/siggnd...
👉 Two 4 Layer PCB Stackups With 50 Ohms Impedance: resources.altium.com/p/two-al...
👉 Check Out Our 1-Minute PCB Design Reviews: • One Minute PCB Design ...
👉 Find Zach on LinkedIn: / zachariah-peterson
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Great video! Glad to know more types of stack-up designs.
We also have this video on other 4-layer stackups: ua-cam.com/video/b4ncs8qfAiA/v-deo.html
Then we have this video on some HDI stackups (starting with 6 layers): ua-cam.com/video/8sFIVD5fqfw/v-deo.html
What else would you want to see? 6 or 8 layers?
That was brilliant, thank you! 👏I like this 4 layer stack up idea.
I always will be lover of sig/power - gnd - sig/power - gnd or any variation with L2 an L4 as GND ,the EMI control thats great
uh no.
@@erik3208 If it passes EMC and SI specs then why complain?
i usually use sig-gnd-pwr-sig config but routing all high speed signals on layer 1 and all other signals that don't require special treatement on layer 4
I've done this often for power systems that have some digital interface on them. It's not common but it works and it's nice to have the big power layer for high current.
A video on gnd, sig, sig, gnd could be interesting too
Take a look at this video: ua-cam.com/video/b4ncs8qfAiA/v-deo.html
I might have to try this stackup approach on my next layout!
For the second example high speed board.... If I did fill the top layer to balance the copper planes out, which would require that 3W rule for clearance, would it also be safe to use the impedance calculator with CPWG to ensure the trace impedance stays the same? I guess what I'm really asking is would there be a performance advantage with the ground pour instead of just microstrip referencing L2?
The 3W rule for clearance is more important when a trace requires controlled impedance. Technically it does not have to be 3W in all cases, the actual limit can be smaller and it depends on the Dk value and the laminate thickness. However, 3W is a good conservative value if you do not know how to calculate the limit specifically. If you use Altium you can also just design the line to be coplanar with the Impedance Calculator in the LSM, then it will already account for the clearance value. In terms of signal propagation, there is not really a difference that would be noticeable until you get to GHz frequencies, the line would be narrower in coplanar so that would increase conductor loss.
Hi Zach,
On your white board presentation at 4:50 you suggested that "transfer" vias could provide the path for the signal returns when signals transition from layer 1 to layer 4 or visa versa. Return currents need to find their way from layer 2 to layer 3 as the signal transitions from 1 to 4. Transfer vias connected to GND work well when both layer 2 and 3 are both connected to GND planes as the two planes are directly shorted together with the transfer vias. However, if one of those two layers is PWR, the approach in that case is usually to connect the two planes together using a capacitor on the surface. This shorts the two planes together for AC, but doesn't work nearly as well as grounded transfer vias when layer 2 and 3 are both GND, due to the additional inductance needed to get from the planes to the capacitor on the surface.
In the video how were you suggesting that the transfer vias get connected? Where you suggesting that the grounded transfer vias are connected between the GND plane on layer 2 to a GND fill around the signals on layer 4? I guess that might help if you bring the GND fill on layer 4 very close to the layer 4 signals transitioning between 1 and 4, but still doesn't seem very effective for high speed signals as most of the return current for the signals on layer 4 will be flowing in layer 3, even if the ground fill is close to the signal. Do you agree?
The transfer vias would provide the return path coverage on the vertical transition only, during the horizontal route the power plane would have to provide that coupling. So it's less bad than just having the power plane and no reference conductor for vertical transition, and those vias are basically stubs. If you had some ground pour around the traces on the bottom layer, you can then get even better return path coverage throughout the route and you could connect the ground pour on L4 to the plane on L2 using the transfer vias.
Regarding the connection between the PWR and GND planes internally, usually you would have a capacitor somewhere so it could be part of the return path, but I don't think it closes the loop sufficiently on high-speed signals. You can always use transfer vias anyways because there will always be a capacitor somewhere. Unfortunately for capacitors they don't give low-frequency return path coverage as they have higher impedance, so the lower frequency end of the signal bandwidth might not be sufficiently covered.
And yes I agree all of this is not so great for high-speed signals. This is why in the SIG-GND-PWR-SIG stackup I would say the last layer is only good for slow configuration signals, DC signals, or maybe an I2C bus, anything faster should be above the GND plane.
@@Zachariah-Peterson
Thanks for responding.
It sounds like you are agreeing that the Sig-GND-PWR-Sig configuration is not good for high-speed signals transitioning between layers 1 and 4. I have never heard anyone suggest that using a transfer via that is just a stub (only grounded on layer 2), would be effective at coupling return currents from layer 2 to layer 3. However, I guess there would be some AC coupling from the barrel of the GND via to the PWR plane on layer 3. Have you ever done simulation using a transfer via that is just a stub and found it to be effective?
I have heard a number of designers suggest that the proper approach for this situation is to place a capacitor between PWR and GND right above (or below) the point where the signal transitions, trying to minimize the inductance associated with the mounting of the capacitor. It doesn't sound like you are a fan of that solution, but I suspect that it might be more effective than the stub transfer via approach. Have you done designs using the capacitor and found it to be ineffective?
@@thomasyunghans1876 Yes we agree, the transfer via is only effective near the signal via, everywhere else you rely on the capacitance between PWR and GND. If you have some discretes around, that helps but who knows where those discretes are located or which one provides the greatest return path confinement, so even with those discretes you could still have a bigger loop inductance. You could also place a capacitor right where the signal transitions, but I'm not a fan because it's impractical. Who wants to go back through a board, locate every signal via, and add another capacitor right at that point? It's too time consuming in my opinion, if I know I'm going to have to route high speed between both layers I would prefer to do the stackup correctly to begin with, or just put ground pour around those signals adjacent to PWR and then use the transfer via.
Hi Zach, what do you think about this kind of stack up: SIG/PWR&GND/GND/SIG. Could I use it considering that I don't route over the splits?
We have seen this implementation in one of the 1-minute design reviews. If you can do it without routing over splits then I say it is fine. I think it takes more planning to do it correctly but it can work well.
@@Zachariah-PetersonBeen looking for this answer all over. Thanks!
If the analog signals are very low level and require shielding, do you think
L1 Sig/pwr
L2 Gnd
L3 Analog signals
L4 Gnd
Is the best approach?
Yes this is a good approach and I think we received a design review submission that used this approach. It is just like you say, the ground planes above and below the analog signal provides shielding against noise and isolates it from the other signals on the top layer.
Ever since the cheap rapid fabricators made 4-layer stackups readily available for hobbyists, I've been hooked on signal - ground - V+ - V- for my audio boards. "Power rail impedance? What power rail impedance? [evil grin]" Rout the signals on top, pop in vias for the power rails and ground where needed, Bob's your auntie. Powered from a single 9V battery? No wuckers - Vref is the new ground. All discrete transistors and no need for split rails? Might as well make both inner layers ground and the bottom V+. SMD boards using this stackup look positively naked on the bottom. If I'm the least bit clever about my component placement, I hardly ever need a trace to jump layers; when I do, there are zero ohm jumpers - that's what they're for.
That's a really good idea for audio! Especially with power, with the +V and -V on two layers you have a lot of room to widen out the traces when needed. You should send me an example board, I'd like to see it.
@@Zachariah-Peterson "Nothing to see here; move along." ;p V+, V-, and GND/Vref are solid planes, only interrupted by the vias. As Dave Jones of EEVblog has said about cheap pocket moldymeder teardowns, "We've been mooned!"
I mostly just do small signal preamp-y stuff these days (distortion effects, cab simulation), so the signal traces are pretty much just 10 thou across the board. If I need a power amp, off-the-shelf Class D amplifiers are so good and cheap these days there's little sense rolling your own analog amp. I'd be happy to dig something up for you though.
How to submit PCB for 1 minute review? @Zach
Thanks
Reach out to Zach on LinkedIn to have your design reviewed: www.linkedin.com/in/zachariah-peterson/
I did follow Zach on LinkedIn, indeed he does scroll a lot lol
I wonder why people breaks a 50 Ohm trace route with a 50 Ohm resistor (a design sample #2)? It should have no effect at all. I think all we need is to match an input impedance with a line impedance. A resistor and an in series capacitor to a ground just before a connector/IC input is fine even for a weakest CMOS output. Am I right?
It does work as you say but only with the output impedance of the buffer being exactly zero, or at least very close to zero. If the buffer does not have an interface standard or standardized impedance then the trace can be something other than 50 Ohms, it is not always the case. That built-in source impedance and the series resistor together set the output level to the desired value when viewed at the load. Here is a video about it: ua-cam.com/video/pL6dY5VKwMI/v-deo.html
@@Zachariah-Peterson I think we need to match a trace and an input impedance to reduce reflections. We don't care of a source cause it will produce "some" level, but this level will be without ringing. At least AMD is fine with only an input impedance matching. "Your" output 50Ohm will be added to a pin output impedance, and so.. What a final impedance will be in this case? For sure it will be far from 50 Ohm. I consider a trace as that resistor.
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