Should You Put an Inductor Above Ground? | PCB Layout
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- Опубліковано 31 тра 2024
- One of the questions Tech Consultant Zach Peterson frequently encounters is, "Is it okay to put ground below an inductor in a switching regulator?" To answer, Zach dives into noise generation, interference, capacitance, and more.
0:00 Intro
0:43 Noise Generation, Interference, & Switching Regulators
2:49 How Noise Arises
6:27 What about the Cutout?
9:34 Capacitance between Ground and the Switching Node
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I've heard the phrase: 'If you don't know how to do ground right, just put lots.'
That's the mantra I live by.
I absolutely agree eventually it's going to choose the path where it 'see' the lowest impedance.
Unless it's best to separate the switching 'ground' currents from the 'signal' ground currents.
I once troubleshot a design where a current sense amplifier output was sometimes indicating 5-15mA over current....I eventually noticed on the PCB layout files that while the schematic showed a separate wire for the low-side input of the current sense amplifier, the net name was still 'Gnd' and the via which the designer intended to use to route the separate signal sense line on an inner layer, instead connected directly to the ground plane which had other power currents flowing which produced a significant offset voltage on the amplifier's low-side input.
But, still if one doesn't know how to 'do ground right' well, that's just one of the things that can happen. ;-)
My old professor used to say, it isn't true if it isn't measured. It should be easy to do a test board with all the different options and measure the effects. No need for speculation.
Well since you bring it up, I designed a test board for this with three copies of this regulator circuit and it came back from fab last week! We'll be doing a video showing testing soon so stay tuned. Also, there was just recently an article by Ken Wyatt and Steve Sandler in Signal Integrity Journal that did some tests of this and came to the conclusion that ground is generally preferred at MHz and higher frequencies.
@@Zachariah-Peterson That will be interesting.
The capacitance on a net is way less than an external FET gate capacitance. Power conversion, sure you might take a bit but it is crazy small. Ground under the inductor and keep the ground from the output cap, IC PGND, input cap, and GND for external FETS (ignore if internal) in the same ground, with a single connection to main GND. This keeps the current loop inside of the local GND and any inductor noise will stay inside as well (within reason). Good technical video, I enjoy these, you never know, you can always learn something.
Another great reason we should NOT put a cutout below the inductor is so we can provide a solid, continuous return path for the switching current in the inductor. Any cutout will interrupt the flow of the return current that WANTS to flow directly below the inductor.
However, in my designs, the copper that i do remove is the one below the inductor, but on the same layer as the inductor pads since this ground fill between the pads may create unecessary parasitic capacitance that could affect the inductor value.
TLDR: cutout on 1st layer, solid plane on 2nd layer for me
I do the same thing: Remove planes in the closest one or two layers. Keep the plane in the other layers. As often recommended in small regulator datasheets.
The 1-10nF MOSFET capacitance mentioned in the video is for big 10A regulators. Small 500-1000mA regulators are less than 20pF.
This actually makes sense: It is typically small regulators which have the GND cutout recommendation in the datasheet, while high current regulators don't have that recommendation.
The current through an inductor is by definition low dI/dt. Which makes the return path less important regardless.
Has anyone actually built two versions of the same circuit, one using cut out and one with solid plane, and carefully measured and documented the performance of the regulator and the conducted and radiated effects? Given the price of 2 and 4 layer pcbs, this would be straightforward and could put the issue to bed for good. "I've never had a problem doing this or that..." is meaningless without actual data, including the switching frequency and currents.
Sounds like a great idea for another video....
Yes, there is video - ua-cam.com/video/q0oH-nV3dpI/v-deo.html and article
Outstanding! This aligns with my intuition and common practice about these things but I’ve never thought it through quite to this extent. Many thanks Zach.
Wonderful!
Rick Hartley has a great presentation on Altium Live about field containment and proper shielding. It applies here as well.
Always have a solid ground under the switching power supply. Most importantly try to provide a low inductance GND return path (preferably on the same layer) from the output caps to the switch GND pins to keep current loops as small as possible. Tie this GND return to the GND plane AT THE SWITCHER and not at the output caps.
Try to place switching power supplies away from sensitive circuits and avoid routing high speed digital signals or sensitive analog signals underneath a switching PSU.
But isn’t we are buying +-20% inductor?
@@gn_ghost4757 It’s not about accuracy of the inductance, it’s about shielding against stray flux and minimising impedance in the high current/frequency paths to maximise performance.
I am enthusiast, and a such kind of study is so helpful! Thank you!
Nicely explained!
Great video, easily explained!
Glad you enjoyed it!
Great subject. Great video. Keep up the great job!
Much appreciated!
Great explanation. Thank you
Glad you liked it
Hi Zack, your videos are always interesting and well done.
You could make a guide or a small manual collecting all the notions you presented in your videos. I would purchase it 😉
Follow me on linkedin, when my courses are finished you'll be the first to know
Noted!
Hey, there's a full differential amplifier from TI that's got the weirdest recommended layout. On a four layer board they've avoided ground under the device. The part is THS4551. Your explanation/critique could make a good video.
I'm looking at the datasheet and I second this. The first bullet point in 12.1.1 Board Layout Recommendations states
> When the signal goes to a resistor, parasitic capacitance becomes more of a band-limiting issue and less of a stability issue.
The example applications are a all filters with frequency plots from 1kHz to 100MHz, so impacts on frequencies seems crucial for this part.
@@Ziraya0 The THS4551 is a higher frequency (getting close to RF) diff amp, and is not an apples-to-apples comparison with a switching regulator inductor. For instance, the THS4551 is not an EMI offender, but rather would need to be protected from EMI since it is a noise-sensitive component in the analog signal chain. Also, any reduction in capacitance at the pads (pF matter here) of the IC is going to help the frequency response of the designed filters.
Most high speed op-amps have ground cleared under the pins and feedback nodes at the very least. Any parasitic capacitance can cause instability in high-speed high-feedback amplifiers.
The SMPSUs usually use an RC oscillator to adjust the frequency with a very small capacitor like 470pF or smaller. Can this extra capacitance (from the GND plane) influences the oscillator's frequency?
If the unit you are using has the driver and switching elements in an integrated circuit that uses an RC oscillator, then no the excess capacitance won't be noticed. If you're using discrete components then maybe it will be noticeable, but at that level you will have separate gate drivers, a current sense amplifier, and probably a controller with a feedback sensing mechanism, it all tries to compensate for deviations from target oscillation freuqencies and power output values. Even in those cases the capacitance in the switch node will probably be small so I would not expect it to affect the frequency significantly, and even if it did the feedback tracking in various portions of the system would probably compensate for it automatically.
That bit of parasitic capacitance you pointed out looks like a free snubber made from a nearly indestructible parasitic capacitor.
I have done couple of boards with switching regulators on. Normally my boards have a solid ground plane on the second layer from the top/bottom. A lot of my boards are micro via, which makes the substrates between the layers very small. The reason I would remove the ground plane below the inductor, especially on the switching pin to the inductor is to minimise the capacitance, as the switching frequency would be influenced by the additional capacitance. On the output of the inductor the added capacitance is welcomed, and I never remove the ground plane from there.
I have seen that practice as well. For a 1 sq. mm pad size on 3 mil thick dielectric with Dk = 4, the parasitic capacitance for that pad is only 0.4 pF, so it's really small! It will be much smaller than most FETs. However, the inductance of that leftover hole would also be very small so I would expect small mutual inductance with respect to the high side of the inductor. I would suspect there is probably not much effect but if there is data out there to show differently then that would be interesting.
That's where this presentation is wrong. It says the capacitance is so low it will not interfere. However, you will see it does matter if you calculate the capacitor impedance. It would be better to learn people to analyze their boards instead of trying to provide some general rules.
good topic. what about Ethernet Iso Transformers? Or CMC ?
This is a good question. I wrote an article in Signal Integrity Journal about this specific topic. I'll do a video on it.
YOu mentioned the level of paracitic capacitance of the PCB board , but what's the eddy current level or opposition flux ? what extend of impact is it gonna have to reduce the inductance effectiveness after we give such a small area of cutout under the inductor?
It depends on the edge rate of the switching waveform and the size of the induced current. It also depends on the geometry of the copper, it is actually quite difficult to calculate and would require an electromagnetic field solver. There is an article in Signal Integrity Journal that looked at emissions from the cases with solid return plane vs. plane with a cutout. They found that at frequencies above 10 MHz the presence of the plane produced lower emissions compared to the case with the cutout. The article is titled: DC-DC Converters - Solid Return Plane or Cutouts Under Switch Node and Inductor?
no cut out ever in switching regulator circuit but I use cutout in RF filtering circuit.
With the cutout, you draw lines going all the way around and into the hole, without the cutout this path has a lot of shielding in the way, does that force these field lines to take a shorter route to like the shorter ones? Is that, and I have no understanding of this, good?
I draw it like this because the magnetic field always involves closed loops, and assuming the conductors are perfect there would be no normal component of the magnetic field (it would be canaceled by the eddy current). This means the conductor would distort the magnetic field so that it maintains a closed loop above the board.
Hi, does this work same for POWER transformer? ( use for isolation in dc-dc convertor consider a PSFB)
Essentially yes because transformers are just inductors that share a magnetic material as the core material. However it's important to note that transformers are normally oriented such that the field lines run parallel to the top surface of the PCB and will already form concentric circles, so the field line drawing does not exactly apply to all transformers. Also power transformers are normally used in applications where you need galvanic isolation (such as an isolated power supply), this means you have a ground split somewhere in the board, and that ground split is usually placed right near the transformer.
Yes there is a split in ground but I saw some vias under the Tesla charger Transformer (It is a 10:12 Transformer which is multiple PFC voltage by 1.2 ). Or maybe those are not via but look like some of them (I can not post a pic of it in here) in our design it is a PSFB topology used for OBC (OBC: On Board Charger), two grounds are away from each other and just in some small area connected with MKT capacitor to chassis total power of each module is 3.3KW and in total having 3 of them parallel and we get 10KW power but there is no clue that, Is our grounding okay?(because we do not have EMI problem in here, because no one check it!) but there is some inaccuracy in sensor measurement and problems with IO of PC when OBC work with its full power (i.e 10KW) and probes show the large switching noise from Transformer and inductors which are toroid. thanks to the advice the revision have better condition but Transformer is still noisy💀.
Thanks for replay it is mean a lot for us.🙏🙏
@@Zachariah-Peterson
If there is a complete GND copper foil under the inductor, can traces be routed on the next layer of the copper foil?
Yes, that is the reason we interleave ground between signal layers, so that the layers are isolated from each other.
@@Zachariah-Peterson Thanks!
Should I put the inductor close to components like integrated circuit to reduce noise from tracks ?
The best way to reduce noise injection into nearby tracks is to put the inductor above ground and to make sure the current loop through the inductor to the output terminals is as short as possible.
@@Zachariah-Peterson do you mean that I have to put a ground plane under the inductor in the top face and bottom face?
@@haythemjelassi4766 You don't have to put ground under the inductor, the circuit will probably work without ground but there could be excessive noise on the output and excessive radiated noise depending on how you laid out the board. The radiated noise could be strong enough that you violate EMI limits and your product does not pass EMC testing. This is important because if you want to sell a product to the public it needs to comply with EMC regulations.
I was searching for how shield reduce inductance of air core coil used in my circuit.
And from paper "Effect of a Conducting Shield on the Inductance of an Air-Core Solenoid" it looks like proper shield should be huge.
For example, if diameter of shield is twice the diameter of coil, inductance reduction is ~15%, for thrice diameter, reduction is ~5%.
Of course, coils with ferrite core will behave differently, but what I learned is that it is not that easy to properly contain field of a coil.
Yes that is true, shielded inductors help contain the magnetic field but it is not a perfect shield.
@Altium Academy: Placing the ground plane below the inductor reduces the value of the inductance itself. Is this true ?
I think that is what he was saying when he gave values like 1-10nF and 10-100pF ... yes, it reduces the inductance, but on the order of 1%, so maybe even less than you're losing in other ways by not having it.
@Jim J. Jewett Those numbers were in reference to the parasitic capacitance created by the nearby ground, which would theoretically reduce power conversion efficiency if that capacitance were large because some power would be diverted away from the inductor. So you have to compare to the rectifying current path and the output to determine if there is enough leakage to produce considerable reduction in power efficiency at the switching frequency. Since the FET has higher capacitance during charging it will control the switching current path by providing the lowest impedance to the switching node and the inductor.
He said that, those magnetic lines which escapes from the ferromagnatic core (they don't really want, but in real life they will) create eddy current in the copper traces, what will create opposite magnetic field (Lenz's law) which decrase the inductance. So this only applies for that part of the inductance what came from the air around the inductor, which is not too much.
I believe that magnetic fields of inductance at low frequencies up to 1 MHz do not have any effect on the tracks on the printed circuit board, since copper has low magnetic permeability and is not a magnetic conductor, the magnetic field passes through the copper tracks.
If this was the case, how could crosstalk between traces be possible < 1 MHz?
@@remy- This frequency was given conditionally. At low frequencies there is a magnetic field and an electric one, at high frequencies it is already considered to be homogeneous. Copper and other materials with low magnetic permeability are absolutely transparent to the magnetic field, but the electric field still affects them and interferes, but it is perpendicular to the magnetic field, if what you drew is called an electric field, then this theory works, but in sources power supply frequency is usually less than 1 MHz, so these concepts should be separated there.
The point is that with copper we get shielding on electric field, but not magnetic field (which would result in eddy current )?
@@remy- At 1MHz sine wave? Or do you mean 1MHz digital? Digital rising edges in the MHz contain waves in the GHz.
Can this be applied to common mode chokes? Just curious
Yes because a common mode choke is essentally just a pair of inductors. The coupling is the same as you would observe in a transformer, just typically at smaller scale. The difference with common-mode chokes and transformers is that these components attempt to confine the field inside a magnetic core to ensure maximally efficient coupling (i.e., low leakage inductance). Because of how the component is designed you intend to not have much leakage of the magnetic field so you would expect less of an impact compared to an individual non-shielded wirewound inductor.
@@Zachariah-Peterson Thank you very much for this info Zach!🫡👍
I thought the main argument for not filling ground under inductors was neither of these.
At higher frequencies the parasitic capacitance from SW to the output side of the inductor would increase. This due to the presence of copper essentially between them--so the two capacitances from each inductor node to the poured copper, in series.
Essentially, this lowers the SRF of the inductor.
I rarely/never do this as i havent found it necessary, but ive always considered it a reasonable approach.
Capacitances in series (in this case mediated by a conductor) will decrease the capacitance, not increase it. For the SRF of the inductor, I have not heard about the lowering of SRF but you could infer something like that by comparing the winding capacitance to the mutual capacitance between the pads. Typical values of winding capacitance are between 1-10 pF on a large inductor, i would expect very small pad-to-pad mutual capacitance on a large inductor, so the mutual capacitance would add some capacitance but you might expect small effect in some packages.
You state that the magnetic field is redirected by the copper, but the relative permeability of copper is ~1, so I think that the magnetic field passes through the copper unaffected.
I meant by the eddy current induced in the copper, but you're right copper has low permeability and is non-ferrous.
After researching some more, it seems some of the AC component of the magnetic field gets cancelled out by the opposing magnetic field generated by eddy currents on the copper plane. I would be curious to see the math or simulations showing the field lines at different frequencies.
The best reason I find for not putting copper under an inductor is assembly. Other than this, there should be no real influence as long as the switching power supply is separated from the rest of the design at the input and output capacitors' pads. There should be a cutout in the copper that allows current flow around the pads only and the EMI problem is solved.
How does copper under the inductor affect assembly?
@@ytpeep7393 It's the thermal mass I was thinking about. The inductor has a big amount of thermal mass and the substrate underneath has also a big amount, both being mostly high thermal resistant materials. There is the EMI too which should be considered when we think about inductors.
Doesnt inductors come in a torroidal arrangement?
They come in many arrangements, we show several types at about 1:40 in the video.
Rather than have a copper cut out in the ground plane, could you have unconnected copper in the ground layer where the eddy currents are induced to shield the lower layers? Follow up question: would connecting this new polygon to one side of the inductor have any benefits or consequences?
If you have unconnected copper that will effectively become an antenna (a poor one, but an antenna nonetheless) because the induced switching currents have nowhere to go but radiate outwards. A floating copper area (not connected to anything) is a very poor EMI shield.
In general you should not have large unconnected (i.e., floating) bits of copper around the board because they can act like antennas. Because charges can move freely in conductors, they will easily oscillate in the presence of an electric field (this is a displacement current), in and the electric field source plus the floating copper become a large dipole antenna. This then radiates around the PCB and can create noticeable emissions in EMI testing.
I think copper is not ferromagnetic and hence, it is useless shielding magnetic fields created by inductors. The most practical way is by using shielded inductors (which use ferrite or other ferromagnetic materials). The major reason to wanna place ground planes underneath is to reduce the current loop of the switching node.
It's been awhile but I believe I mentioned the current loop of the switching node in the video and it does not have enough capacitance to bypass typical power MOSFETs. Also copper is diamagnetic and is slightly opposed to an incoming static magnetic field, but that is not the mechanism by which shielding is provided. Eddy current formation is the physical mechanism responsible for this.
How they made cpu DIE 😳😳