Verilog® `timescale directive - Basic Example

I show Verilog® source code that includes a `timescale directive and a testbench module containing a single delay statement. I explain how the compiler uses the arguments of the `timescale directive to translate the delay magnitude into a specific time duration. A simulator would use that time duration when simulating the behavior of that module.
The 1st argument to the `timescale directive is called: time_unit.
The 2nd argument to the `timescale directive is called: time_precision.

[@abdosalah22]

Great explanation!

[@madhumitamahapatra3277]

Hey sir ,
From wherever you are, just a bundle of Thanks to you sir🙇🙇, u cleared my doubt in just two minutes ,. and before this video I spend my nearly 1 hours to understand it 😅

[@danny_racho]

How is 20ns closer to 15ns than to 10ns? It's the same distance. Can you elaborate further?

[@cricupdates6365]

What if the precision time is in picosecond, how do we round off then?

[@afzaljunaidi8157]

I always had doubt about precision
How it round up
Now I understand thank you mate

[@manojharshavardhan2385]

it was a fine video
Thank you

[@joffinjoy555]

Good explanation. Thank you

[@sksameer208]

Nice Explanation

[@amey4996]

Fix the audio problem I can only hear on left side of headset

[@nabzero6528]

is this how to make duration for an on statement?

[@RyanThompsonrthomp]

Beast explanation

[@asictronixdt4953]

Good explanation but please fix the audio. Can only hear from left speaker

[@amey4996]

Same

[@maheshreddy6994]

Good explanation ,Thank you