Timescale in Verilog | System Verilog timescale | Compiler Directive `timescale | Verilog Time delay

[@Electronicspedia]

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[@preetamdewangansirclasses2502]

sir $realtime will equal to 15.6 ns only. $time will be equal to 16ns.

[@Electronicspedia]

Yes you are right. Thanks for highlighting.
$time returns the integer value and $realtime returns the real number. 👍👍

[@rahulbhadoria_1161]

Thank you Sir for this simple explanation 👏👏🤗

[@Platica.Vasile]

Thank you for the quick video, but for a more thoroughly you should corelate this with a timer to see exactly how the timescale affects the program.

[@nenadmilutinovic4752]

Hello Sir, what will 15.5 be rounded off to? 16 or 15?
Thank you in advance!

[@RanjanSingh-pm6ze]

Sir if possible then please make a playlist on system verilog. Because there is no one at UA-cam who is teaching like you. Everyone is using just ppt for teaching purpose. Even there are many famous institute they are just using ppt.

[@Electronicspedia]

Thanks for your compliments. Sure will do system verilog concepts.

[@preetamdewangansirclasses2502]

sir kindly extend this discussion considering ps as a precision

[@pushpendranayak3235]

Nice