Verilog Tutorial 3 -- `define Text Macros

[@timmorgan3673]

Great stuff - Cheers :)

[@deepakgurunthu2621]

Nice work. I finally connected the pieces regarding using `define and `ifdef in Verilog.

[@Edaplayground_EPWave]

Recommend viewing in 720p quality or higher.

[@AmanKumar-ph4my]

how to create macros in which we are calling function realtime type from class a in system verilog

[@adityaraja8276]

If i want to write an if else staement in user defined macro for function(here ADD5), can I do it. It is throwing me a syntax error.

[@matthewtaylor9727]

You ought to be able to do it. Can you post the EDA Playground URL of your code?

[@karthikkotebagilu3421]

Can we pass macros heirarchically like parameter?

[@Edaplayground_EPWave]

No. Macros are so-called compile directives. They do not fit in the the Verilog/SV scope. So, if you define a macro in one module, it is visible globally: www.edaplayground.com/x/fkMB . So, passing a macro hierarchically like a parameter doesn't make sense.

[@karthikkotebagilu3421]

@@Edaplayground_EPWave I wanted to to understand this:
Consider I have a module_A with different compilation statement based on MACRO1. Can I have two instances of module_A in my top file - one instance with MACRO1 and another without MACRO1? Is there any ways of doing it? Thanks in advance...

[@Edaplayground_EPWave]

@@karthikkotebagilu3421 I can't think of way. This sounds like it might be an "XY" problem (a problem where we spend time focussing on a specific solution to a more general problem, when the specific solution is not a good solution to the general problem). What are you actually trying to do?