This video tutorial series is very helpful for beginners to Verilog. Your creation EDA playground is a great effort for Verilog users all around the world.Thank you very much for sharing your knowledge with others in free basis. Salute you
I'm not sure what you are asking. Blocking and non-blocking assignments behave differently as the video and EDA Playground example show. There are strict about which to use where in an RTL design.
@@orzAR26 I can't make it work with Icarus Verilog, but if you change to Riviera Pro and add "+define+NONBLOCKING" to the Compile Options, you will see (by looking at the code) that non blocking assignments are used and e does change at 5 ns, illustrating well the difference between blocking and non-blocking assignments.
Hi, The value of a is 1'bx on all the simulators on EDA Playground. However, this is NOT for the reason given in the video: the second assignment to a overwrites the first - there is no contention. Instead, at time 0, a initially has the value of 1'bx and the value of 1'bx+1 is 1'bx. Matthew
Very difficult to see on my screen too, text is too small. But I pressed Ctrl and "-" key at the same time, it shrunk the surrounding and enlarged the video portion of the screen, and then I could see it clearly.
I didn't write this code. I can see it could be confusing. They don't have to be the same name. The first name is the name of the module being instantiated (eg Intel i7); the second is the instance name (eg IC3).
Thanks a lot. EDA playground and your playlist are amazing!
That's most kind.
such an amazing video. You break things down very carefully and make sure to explain applications of each example. Thanks so much for this!
This video tutorial series is very helpful for beginners to Verilog. Your creation EDA playground is a great effort for Verilog users all around the world.Thank you very much for sharing your knowledge with others in free basis. Salute you
Recommend viewing in 720p quality or higher.
Probably so you can read the text.
Would be better if see it on 150% zoomed window.
Thanks for the video, however I would like to have seen something on best practice on when to use each type in the real world.
Thank you for the video. Very well explained.
Thanks for taking the time to explain this, very helpful.
Regards,
Sakis
Very helpful thanks!
Excellent learning experience. Just not sure why do you use "output reg [3:0] f, g, h" instead "output reg [2:0] f, g, h"?
(a very late reply) Victor has chosen to demonstrate using 4-bit wide nets and variables. I don't know why. Why do you think 3-bit?
your videos helped me a lot thank u so much sir
thank you
I found this video helpful, thank you.
What happens when blocking and nonblocking assignments are intermixed?
I'm not sure what you are asking. Blocking and non-blocking assignments behave differently as the video and EDA Playground example show. There are strict about which to use where in an RTL design.
he is a god
what is the use of ifdef ?
www.asic-world.com/verilog/compiler1.html
thank you fir eda
You're very welcome.
How to make e work from 0
When d is made to wait 15 ns
Sorry. I don't understand your question.
U made d start after 15 ns
When u coded e to start after 5 ns
But it started to proceed after 15+5=20ns
How to make e to start from 5ns?
@@orzAR26 I can't make it work with Icarus Verilog, but if you change to Riviera Pro and add "+define+NONBLOCKING" to the Compile Options, you will see (by looking at the code) that non blocking assignments are used and e does change at 5 ns, illustrating well the difference between blocking and non-blocking assignments.
This was actually cofusing.
At 4;40 video time value of a should not be 'x'. at simulation time 0, a
Hi,
The value of a is 1'bx on all the simulators on EDA Playground. However, this is NOT for the reason given in the video: the second assignment to a overwrites the first - there is no contention. Instead, at time 0, a initially has the value of 1'bx and the value of 1'bx+1 is 1'bx.
Matthew
hardly can see the words in the screen
I don't know why that might be. It looks fine on my screen (when I make it full screen).
Matthew
go to the video settings (the small gear icon, bottom-right corner of the video window ) and set it to 1080p HD
Very difficult to see on my screen too, text is too small. But I pressed Ctrl and "-" key at the same time, it shrunk the surrounding and enlarged the video portion of the screen, and then I could see it clearly.
Ok awesome
why did you use "dut dut", it may appear confusing to beginners. do they have to have the same name? can't it be "dut xyz"?
I didn't write this code. I can see it could be confusing. They don't have to be the same name. The first name is the name of the module being instantiated (eg Intel i7); the second is the instance name (eg IC3).