I wished you have more content on Verilog to show. The Professor I had in my university for Verilog was a new professor and he made my Verilog experience awful. I hated Verilog. This video explains in detail with examples what is going on at each step. The Professor I had just read the slides and race through the lectures just so we can be up to date with the schedule on his syllabus. Your Verilog lecture is much appreciated.
I know this video is old, but man, thank you, that helped me a lot with my project. After 5 years, this video still helps people out. Thank you!
I wished you have more content on Verilog to show. The Professor I had in my university for Verilog was a new professor and he made my Verilog experience awful. I hated Verilog. This video explains in detail with examples what is going on at each step. The Professor I had just read the slides and race through the lectures just so we can be up to date with the schedule on his syllabus. Your Verilog lecture is much appreciated.
Thanks man. but it would have a little bit more helpful if you had run the code and showed us the simulations.
It'd be nice to extend this testbench, to include the expected result, and to compare them.
Thank you so much!!. After seeing this I implemented my first code in verilog :)
Great explanations, thank you
helped me a lot it would be great if you make more videos
I love your tutorial. Thanks!
Still relevant in 2021....
Very instructive! Thanks!
nice to know about those moooooohnitor statements ;-)
Thanks, it helped a lot
sas
Thanks, it helped a lot