Відео

謝謝啦!

I wish I were there with you.😁

OOPS, I could misnamed the title. However, I have similar videos for you, e.g., ua-cam.com/video/kJmn0uXIewA/v-deo.html I am also working on the extreme SD and is to be published soon.

glad you like them..I love it too!

WOW, thanks!

E_FS沒有align E_CNL是正常的，只是Surface states 會因此帶電，建議找ref. (Kuhn)來看，她說的比我嚴謹多了

好的，我會找那篇paper來看看，謝謝老師!

@@lirunogo She is a very smart lady. Super tough as well.

1. yes, b/c CNL (no Eg) at the surface 2. SS should be < 1nm, it's a "surface". one layer of atom is about 0.3nm 3. The beauty of nature

了解~謝謝老師🕴️

@@lirunogo 歡迎多問

GaAs, AlAs etc.

Planar type: yes, you need HR GaN for reducing leakage, bu not so for vertical devices, you need very good BSM (backside metallization) ua-cam.com/video/8hS0hbBP9Kw/v-deo.html

@王不老說半导 So, the structure is Metal/SiN/AlGaN/GaN(drian and souce are ohm contact) from top to bottom, but for vertical GaN, it is Metal/AlGaN/GaN/Buffer..., isn't?

@@xyzmafour7207 GaN is more complex = GaN Channel + HR GaN...(high resistance)/Buffer/sub., Vertical GaN: see www.mdpi.com/2072-666X/14/10/1937

Will try, the info mentioned is a bit outdated. I need to include Notebooklm...

文中沒說電子的傳導率，只說的是熱傳導係數，有小口誤，牆高很薄，當然就可以穿透.

謝謝啦!

Thanks, glad that you like it! best wishes!

高手，感謝解惑，Robert Chau (my dotted boss in Intel) 研究此材料一輩子，選擇HfO2其實乃是試了許多，結果只有此材料比較好，期間甚至想放棄(imec 寫了一堆論文說絕不可能成功)，最後發現其defect bands not too bad and can be proteced by SiO2 IL.亦即reliability OK，every other oxides failed

Good inputs, can you be more specific, e.g., which page and topic?

hahaha, you are the one appreciate the weirdness in me. Thanks, i like it! Enjoy them, my friend, hardcore science can be fun as well.

good to know that you like my previous videos. Enjoy them!

Glad that you enjoy viewing them. I enjoy making them as well. My goal is to teach engineers in this field from all aspects of knowledge in a fun and entertaining manner. I live in Austin and am teaching remotely as a professor of NTHU_CoSR. I do not have an English nickname, but you can find me in my LinkedIn: www.linkedin.com/in/wei-e-wang-4911533/

glad you like them

glad that you like them:)=

基本上，網上是找不到的，我個人是想以後會製作相關視評的，但是常被其他看到的新東西分心，我建議你應該先了解統計分析，那才是真正的基本功， 現代工藝最後都必須以統計分析解釋，我做了一系列統計分析，我老王賣瓜，基本可以讓你很快上手的， ua-cam.com/play/PLLqmCVy2iann-kmwLvFN3hzY-nRfUy95i.html

@@王不老說半导 多謝前輩。我一直有在反復看前輩製作的統計基礎視頻。

​@@tracygao169 good, did you actually run a statistical SW for practice? BTW, 個人以為，要了解全製程(如果想了解14nm/7nm/5nm這些製程的FEOL/BEOL流程?)，題目有些太大，很容易迷失， 建議你必須找到一個突破點，就是一個重要的與你有"切身興趣的主題"，你想法子去了解所有相關細節(包含如何DOE)，所有歷史及現在進展的"理由與結果"，一直專研到，你可以看到一論文，能夠知道其可行性，大概就厲害了，以此演再看此製程之其他延結部分，此招曰之"見縫插針，以點突破"，然後再擴面，方可知全貌， 建議多利用AI: Perplexity.ai，他推理不見得對，甚至很多有錯，但是挖掘references,一流也 簡單的說，你必須先是某主題的Content Expert，以此建立一種"信心"，再往其他主題，就容易多了!

@@王不老說半导 多謝前輩指點。學生之有用過JMP做一些簡單DOE，用來指引CVD機台的工藝開發。後來看了前輩的DOE視頻以後，加深了一些理論上的理解，也自學了一些統計知識，現在用DOE工具指引工藝開發更有感覺也更加有效率了。我本人也不在fab廠，所以對製程flow之類的知識了解的也比較少啦，就想多學習一下。感覺工藝開發這些東西後面應該都會被AI取代，所以可能需要拓寬自己的知識水平，提升工程能力，才能繼續在這個行業待下去？

@@tracygao169恭喜你走向正確的路! AI太恐怖，我們不是直接被AI打敗，而是被那些善用AI者打敗，所以你要成為善用AI者也!

glad you like them. I like them as well.

哈，ASML TD Director is my old friend. I know.

也許，所謂英雄造時勢，時勢也造英雄啊!

看來你對台積有些成見，若台積不靠一些生態圈幫忙，全靠自己及國外廠商的幫助，那麼就和三星，英特爾相同(英特爾得到國外廠商的幫助更多)，那麼台積也太厲害了一些。

The links are in the presentation (bottom of each page). Let me know if you want a specific one.

Thanks!

I consider myself a process guy, not a design guy. I approach each topic from process perspective with limited introduction of design layout, except those which can impact processes tremendously. HBM uses regular DRAM except they have to stack them together, say 4,8, 12, etc., by a process called MR. MUF (liquid wax with higher thermal conductivity k) of SK hynix or NCF (better control of a plastic film but lower k) of Samsung, or in the future HBI (perfect world, using tool from EVG or Besi). In addition, the bottom die is critical. TSMC will use their 12nm logic for this. Samsung is far behind in this. DRAM is no big deal, these memory maker can make them with high yield. However, stacking them together using W2W is a yield killer. e.g., the new yield is 80% if the two wafer bonded together using W2W with each having 90% yield. What happens if you have 12 wafers to be bonded together. The total yield could drop to 25%. Stacking is costly. Even you solve the DRAM stacking issues, then the challenge is to put them together without warping or particles since you want 100% yield. The power rating for the crazy AI chips are a round a few kW, they can be hot like crazy. The thermal stress induced warpage is a nightmare...

@@王不老說半导 Thanks a lot, Dr. Wang! Sorry for the DRAM design questions! Exactly due to the large amount of TSV embedded, thermal/power control and more issues for DRAM, some special measures have to be taken to make the DRAM appropriate for HBM applications. I am wondering what are those have been adopted and what are those to be coming. It is very interesting, I guess. Again, appreciate your prompt reply.

@@qz9514 DRAM is super sensitive to temperature. It starts to act weird above 85C. It's dead above 90C. They have to refresh regularly (every 64ms). This means bottom die has to do something just to keep them alive. This adds additional heat burden to HBM. Guess you're right DRAM guys need to do something about this by making some special DRAMs as you mentioned earlier. However, this usually mean downgrading the best best DRAM currently we have. Who is going to come out with this new DRAM in time is a question mark, HK hynix or Samsung? Some of my DFM ideas are discussed here for TSV: ua-cam.com/video/C5juSIAPgZU/v-deo.html&lc=Ugy6YjFBqgwuf8ipG4R4AaABAg The newest DRAM are 3D DRAMs, which could mean more DRAM capability with less footprint. How that impacts HBM4 or higher is anybody's guess.

@@王不老說半导 Thanks a lot, Dr. Wang for the continuing sharing. One thing that I know is that s decreased number of WLs per mat, which makes fewer DRAM cells attached to a BL and reduces BL capacitance. The reduced BL capacitance and the amount of voltage developed by the charge sharing between a BL and a cell increases as BL capacitance decreases, thus reducing the sensing time. This suggests the DRAM for HBM could use smaller MAT size for higher reading speed. The other thing is the real estate management around TSV for HBM interconnection. There shall be a certain exclusion zone around tsmc for DRAM cells due to the possible high strain generated from Cu filled TSV. Here are couple things that I can think about. There shall be more to differentiate the regular DRAM and DRAM for HBM. Thanks.

@@qz9514 Thanks for sharing your keen insights especially about TSV. TSV does introduce extra stress issues. But the stress has little impact to DRAM performance since they already leak like crazy. However, I believe the issue has been captured and solved since TSMC has used them on the current AI chiplets using TSV and HBI, except that they need to include many more DRAM stacks. The learning are to be ported for sure.

I could not find them. Sorry!

多蝦啦! 可以到清大找...或 ua-cam.com/video/YNEHlqkj23Y/v-deo.html

Looks like fancy games people play to get publication. Industry does not like them due to cost and no guarantee that the benefit are still there after all the steps are done.. GaN Dit are so hard to passivate, as explained in the video. I simply won't trust these fancy SC (they tried to get themselves into Si-CMOS process flow and failed)

in mVt (HKMG steps)

也替你高興!

加鋁是論槍打鳥的結果，我和發明人之二，Suma Datta and Uday Shah 聊過此事，Intel CR 此發明做的實在不錯，他們本來也沒有想到鋁有效，鋁的熔點太低(660C)，任何原子在2/3熔點時就會亂動的，對後來製程將有巨大限制的， 至於印刷術是中國發明的嗎? 此討論有意思，沒有人云亦云，可以參考， ua-cam.com/video/UTB9kOIi5MM/v-deo.html

IBM文化本來就不適合HVM，良率沒有高過，然而其原創力與專利，世界第一，確有其厲害的地方， LaO不是成本問題，而是量產時會有其他問題，LaO沒事會自己膨脹的，很麻煩，還有其他..

感謝建議，highl 1st or last is indeed a good story...Vt control is one of the key parameters to be controlled. However, my message is about the thought processes (the role of the demon), not too much about the exact technical content.

Thanks!

Glad you like them!

AI目前是如此，以後很難說!最近的論文宣稱Cereberas芯片運算能力，已經在微觀原子數大大超越以前能力

exactly!

一針見血

妙喻!

100% agreed: 學物理化學 必須要有想像力 是一個必須的技能, 電子 穿梭與chemical potential are linked. chemical potential 的定義，非常有意思的! en.wikipedia.org/wiki/Chemical_potential