Dear Dr. Wang: Very nice learning from you! Is it possible to add one session to describe DRAM difference between regular one and those used in HBM? such as the density, MAT size, TSV real estate rule, etc. Thanks a lot.
I consider myself a process guy, not a design guy. I approach each topic from process perspective with limited introduction of design layout, except those which can impact processes tremendously. HBM uses regular DRAM except they have to stack them together, say 4,8, 12, etc., by a process called MR. MUF (liquid wax with higher thermal conductivity k) of SK hynix or NCF (better control of a plastic film but lower k) of Samsung, or in the future HBI (perfect world, using tool from EVG or Besi). In addition, the bottom die is critical. TSMC will use their 12nm logic for this. Samsung is far behind in this. DRAM is no big deal, these memory maker can make them with high yield. However, stacking them together using W2W is a yield killer. e.g., the new yield is 80% if the two wafer bonded together using W2W with each having 90% yield. What happens if you have 12 wafers to be bonded together. The total yield could drop to 25%. Stacking is costly. Even you solve the DRAM stacking issues, then the challenge is to put them together without warping or particles since you want 100% yield. The power rating for the crazy AI chips are a round a few kW, they can be hot like crazy. The thermal stress induced warpage is a nightmare...
@@王不老說半导 Thanks a lot, Dr. Wang! Sorry for the DRAM design questions! Exactly due to the large amount of TSV embedded, thermal/power control and more issues for DRAM, some special measures have to be taken to make the DRAM appropriate for HBM applications. I am wondering what are those have been adopted and what are those to be coming. It is very interesting, I guess. Again, appreciate your prompt reply.
@@qz9514 DRAM is super sensitive to temperature. It starts to act weird above 85C. It's dead above 90C. They have to refresh regularly (every 64ms). This means bottom die has to do something just to keep them alive. This adds additional heat burden to HBM. Guess you're right DRAM guys need to do something about this by making some special DRAMs as you mentioned earlier. However, this usually mean downgrading the best best DRAM currently we have. Who is going to come out with this new DRAM in time is a question mark, HK hynix or Samsung? Some of my DFM ideas are discussed here for TSV: ua-cam.com/video/C5juSIAPgZU/v-deo.html&lc=Ugy6YjFBqgwuf8ipG4R4AaABAg The newest DRAM are 3D DRAMs, which could mean more DRAM capability with less footprint. How that impacts HBM4 or higher is anybody's guess.
@@王不老說半导 Thanks a lot, Dr. Wang for the continuing sharing. One thing that I know is that s decreased number of WLs per mat, which makes fewer DRAM cells attached to a BL and reduces BL capacitance. The reduced BL capacitance and the amount of voltage developed by the charge sharing between a BL and a cell increases as BL capacitance decreases, thus reducing the sensing time. This suggests the DRAM for HBM could use smaller MAT size for higher reading speed. The other thing is the real estate management around TSV for HBM interconnection. There shall be a certain exclusion zone around tsmc for DRAM cells due to the possible high strain generated from Cu filled TSV. Here are couple things that I can think about. There shall be more to differentiate the regular DRAM and DRAM for HBM. Thanks.
@@qz9514 Thanks for sharing your keen insights especially about TSV. TSV does introduce extra stress issues. But the stress has little impact to DRAM performance since they already leak like crazy. However, I believe the issue has been captured and solved since TSMC has used them on the current AI chiplets using TSV and HBI, except that they need to include many more DRAM stacks. The learning are to be ported for sure.
thanks for this interesting sharing!!
Thanks!
Dear Dr. Wang: Very nice learning from you! Is it possible to add one session to describe DRAM difference between regular one and those used in HBM? such as the density, MAT size, TSV real estate rule, etc. Thanks a lot.
I consider myself a process guy, not a design guy. I approach each topic from process perspective with limited introduction of design layout, except those which can impact processes tremendously.
HBM uses regular DRAM except they have to stack them together, say 4,8, 12, etc., by a process called MR. MUF (liquid wax with higher thermal conductivity k) of SK hynix or NCF (better control of a plastic film but lower k) of Samsung, or in the future HBI (perfect world, using tool from EVG or Besi). In addition, the bottom die is critical. TSMC will use their 12nm logic for this. Samsung is far behind in this.
DRAM is no big deal, these memory maker can make them with high yield. However, stacking them together using W2W is a yield killer. e.g., the new yield is 80% if the two wafer bonded together using W2W with each having 90% yield.
What happens if you have 12 wafers to be bonded together. The total yield could drop to 25%. Stacking is costly.
Even you solve the DRAM stacking issues, then the challenge is to put them together without warping or particles since you want 100% yield. The power rating for the crazy AI chips are a round a few kW, they can be hot like crazy. The thermal stress induced warpage is a nightmare...
@@王不老說半导 Thanks a lot, Dr. Wang! Sorry for the DRAM design questions! Exactly due to the large amount of TSV embedded, thermal/power control and more issues for DRAM, some special measures have to be taken to make the DRAM appropriate for HBM applications. I am wondering what are those have been adopted and what are those to be coming. It is very interesting, I guess. Again, appreciate your prompt reply.
@@qz9514 DRAM is super sensitive to temperature. It starts to act weird above 85C. It's dead above 90C. They have to refresh regularly (every 64ms). This means bottom die has to do something just to keep them alive. This adds additional heat burden to HBM.
Guess you're right DRAM guys need to do something about this by making some special DRAMs as you mentioned earlier. However, this usually mean downgrading the best best DRAM currently we have. Who is going to come out with this new DRAM in time is a question mark, HK hynix or Samsung?
Some of my DFM ideas are discussed here for TSV:
ua-cam.com/video/C5juSIAPgZU/v-deo.html&lc=Ugy6YjFBqgwuf8ipG4R4AaABAg
The newest DRAM are 3D DRAMs, which could mean more DRAM capability with less footprint. How that impacts HBM4 or higher is anybody's guess.
@@王不老說半导 Thanks a lot, Dr. Wang for the continuing sharing. One thing that I know is that s decreased number of WLs per mat, which makes fewer DRAM cells attached to a BL and reduces BL capacitance. The reduced BL capacitance and the amount of voltage developed by the charge sharing between a BL and a cell increases as BL capacitance decreases, thus reducing the sensing time. This suggests the DRAM for HBM could use smaller MAT size for higher reading speed. The other thing is the real estate management around TSV for HBM interconnection. There shall be a certain exclusion zone around tsmc for DRAM cells due to the possible high strain generated from Cu filled TSV. Here are couple things that I can think about. There shall be more to differentiate the regular DRAM and DRAM for HBM. Thanks.
@@qz9514 Thanks for sharing your keen insights especially about TSV. TSV does introduce extra stress issues. But the stress has little impact to DRAM performance since they already leak like crazy. However, I believe the issue has been captured and solved since TSMC has used them on the current AI chiplets using TSV and HBI, except that they need to include many more DRAM stacks. The learning are to be ported for sure.
Great presentation on the business perspective! Refreshing!
😁
Is ADK really becoming a thing? Or TSMC/Intel still largely guide the heterogeneous design and integrations? 🤔
I think so. TSMC has a lot more experience in this than Intel.
張忠謀自己也非常暴躁, 如果不滿意下屬的報告, 常常都是當著員工的面把報告甩在地上. 上行下效, 台積電內部文化跟軍隊幾乎沒差別.
哈哈哈，我知道，因為有許多老友在內工作，但是他對外用的是innovate quietly，姿態很低的! 你看他與BESI合作，偷偷幹了八年，結果HBI (D2W)一舉成名天下知，AI世界無敵手
他對台積電的理解有很多錯誤 聽有用的就好了 剩下的當他鬼扯就可以了
@@Sky94567 有這心態(聽有用的就好了)，也是不錯的，看來你對台積電怨念不少，那麼請問他世界第一是如何得來的? 罵罵部下就可以嗎?
台灣的電子業生態圈是時代造就的 因為台灣本來就是以中小企業為主 跟 韓國以大企業為主完全相反 而 這種以校企業為主的方式特別適合在今日分工細膩的電子產業 不是甚麼台積電創造生態圈
也許，所謂英雄造時勢，時勢也造英雄啊!
我只能說你對TSMC的理解有很多錯誤的地方 首先台灣的電子生態圈不是靠台積電維持 相反的 曾經有一段時間是台積電要求供應商在地生產 類似像現在美國要求台積去設廠一樣 要知道台積電在供應商之間的名聲很差
看來你對台積有些成見，若台積不靠一些生態圈幫忙，全靠自己及國外廠商的幫助，那麼就和三星，英特爾相同(英特爾得到國外廠商的幫助更多)，那麼台積也太厲害了一些。
很多時候經驗只能當作參考...太多魔鬼藏在細節 在這一行很多人以為自己很厲害 但我待越久越覺得 自己不過是知道翎毛一角而已...對於一個無法控制自己情緒的人說有多大聰明才智跟智慧 我看也是很有限
台積跟供應商的關係 很多時候是台積強勢要求供應商配合 根本不是甚麼互相合作 台積唯一不敢得罪的只有ASML...
哈，ASML TD Director is my old friend. I know.
在TSMC的製程經驗完全無法複製到其他公司 晶圓製程研發 不同公司之間有製程不相容問題 連這都不知道的話 不要說自己是做研發的