SiGe B has evolved to ISBD SEG insitu boron doped selective epi growth, no implant at all The epi temperature wise, GeH4 is very active and then lower temperature is good enough In addition you need to avoid Boron diffusion. Higher temperatures are not good for you SiH4 for nSD requires high temp since it’s less active than GeH4 One can use higher order silane or germane but it may be too active and you may have issues with SEG
Dear Dr. Wang, thanks a lot for the teaching. One question like to ask is SiGeB EPI deposition temperature. Since B% is getting very high, I guess, the old approach with SiGe EPI first followed by B implantation is not effective any more. Considering SiGeB EPI process for P-MOS S/D, is there anything change for the NMOS/PMOS order in CFET? Also like to know the typical growth temperature used for all these EPI process, Si, SiGe, SiP, SiGeB etc for source/drain? For different Ge& of SiGe, Is the lower temperature better to achiever high Ge% in SiGe EPI process? So many questions, sorry about that?
Thanks a lot for the detailed explanation. Also like Dr. Wang to explain all the means to control H absorption during EPI growth process other than temperature. Is the H content in the precursor also a part of it? Appreciate
It's part of Epi kinetics. There are many studies about how every element works within the Epi gaseous system (with the surface), e.g., a paper belwo iopscience.iop.org/article/10.1149/1.3548113 However, people are now relying on SW for simulation for a deeper understanding www.coventor.com/paper/influence-of-sige-on-parasitic-parameters-in-pmos/
SiGe B has evolved to ISBD SEG insitu boron doped selective epi growth, no implant at all The epi temperature wise, GeH4 is very active and then lower temperature is good enough
In addition you need to avoid Boron diffusion. Higher temperatures are not good for you
SiH4 for nSD requires high temp since it’s less active than GeH4
One can use higher order silane or germane but it may be too active and you may have issues with SEG
Dear Dr. Wang, thanks a lot for the teaching. One question like to ask is SiGeB EPI deposition temperature. Since B% is getting very high, I guess, the old approach with SiGe EPI first followed by B implantation is not effective any more. Considering SiGeB EPI process for P-MOS S/D, is there anything change for the NMOS/PMOS order in CFET? Also like to know the typical growth temperature used for all these EPI process, Si, SiGe, SiP, SiGeB etc for source/drain? For different Ge& of SiGe, Is the lower temperature better to achiever high Ge% in SiGe EPI process? So many questions, sorry about that?
see my reply o top!
Thanks a lot for the detailed explanation. Also like Dr. Wang to explain all the means to control H absorption during EPI growth process other than temperature. Is the H content in the precursor also a part of it? Appreciate
It's part of Epi kinetics. There are many studies about how every element works within the Epi gaseous system (with the surface), e.g., a paper belwo
iopscience.iop.org/article/10.1149/1.3548113
However, people are now relying on SW for simulation for a deeper understanding
www.coventor.com/paper/influence-of-sige-on-parasitic-parameters-in-pmos/
@@王不老說半导 thanks a lot for the literature sharing
Check out my videos on SiGe epi
ua-cam.com/video/QQJQJf1T-u4/v-deo.htmlsi=VqKaOYMJ6GsD-Teo