SystemVerilog Tutorial in 5 Minutes - 17 Assertion and Property

[@tientranmanh798]

Thank you. I've watched all 25 videos. Your sharing and example are so good. Wish you all the best.

[@openlogic925]

Thanks for the comment! Glad you like them 🙂

[@ragavendraabd-ig1rh]

The way you explain the concepts in the easy way is wonderfull, Your explanation skills are fentastic sir.. Thank you from Raghavendra , India.

[@openlogic925]

Glad it helps. Thanks for the comment 😊

[@silicon_talks]

All your videos are really good. Need more videos for SV and UVM. Thank you so much.
From India❣

[@openlogic925]

Thanks for the comment. I'll do my best 😊

[@tigerchen3808]

May I ask 3:20 when does "disable iff" happen? I can't understand , thanks for your reply.

[@openlogic925]

You can treat "disable iff( condition )" like a normal "if ( condition )". It means if "condition" is true, then don't check. In the property, the condition is evaluated at every posedge of clk.

[@tigerchen3808]

@@openlogic925 Thanks ! I got it.

[@kimongrigorakis]

Thank you very much for your tutorials!! Trully enlightening!
Could you please upload the slides and the code snippets on Google Drive and share them on the video descriptions??

[@openlogic925]

Thanks for the compliment. I'm sorry, I don't plan to share the slides.

[@E4tHam]

Is it possible to do assert final property? I couldn't figure it out

[@openlogic925]

I've never tried that but logically you cannot. assert final is meant to check final resting value (the signal value that finally stabilizes after a clock event), but property is meant to check the stabilized value right before a clock event.

[@Zanzara0403]

Thanks for sharing!

[@openlogic925]

Thanks for watching!

[@notabot1798]

Amazing

[@openlogic925]

Thank you 😊

[@srini.....]

Nice👌👌

[@openlogic925]

Thanks 😊

Where is the next video??

[@openlogic925]

It's still work in progress

@@openlogic925 you are doing great. Please do keep going ;)

[@openlogic925]

@ Thanks for the encouragement 😊

[@AyushAgarwal-YearBTechElectron]

Thanks vro

[@openlogic925]

You're welcome