For the first question, I re-watched the video. I didn't mention any document. So I'm not sure which document you're talking about. For the second question, it's been a long time since I last used Verilog, so I'm not sure if compiler directives are supported there.
Very helpful, now I have only one video remaining. I am going to watch it tomorrow, once again thanks for your series.
Thanks. Glad it has been helpful🙂
Thank you so much for all the videos. Its very helpful to me. Looking forward for more SV tutorials and more UVM tutorials as well!
You're very much welcome ☺
Can't imagine that you can put an extensive-detailed Book Chapter (40 pages) in ONLY 5 mins!
A bunch of thx, Sir!
Good bless you!
Thanks! I'm sure the book covers more. But I do try to summarize the fundamental and the commonly used feature 😊
@@openlogic925
Yup! Sure! But the Book is usually hard to follow and put all things together
Thank you so much for all the videos, you are a great explainer and I hope you keep making systemverilog and uvm tutorials!
Thanks for the kind comment. I'll do my best 🙂
Wow, this section is very useful. Could you please share the document you referred to?
Is this supported only by SystemVerilog, or does it also work in Verilog?
For the first question, I re-watched the video. I didn't mention any document. So I'm not sure which document you're talking about. For the second question, it's been a long time since I last used Verilog, so I'm not sure if compiler directives are supported there.
Sir thank you for all system verilog videos
Please make more system verilog videos for beginners in-depth video with UVM
What you mention at 1:29 is called an "include guard".
Thanks. I never realize there's a term for it.
@@openlogic925 Good concise SV & DIMM background videos. Not a fan of the SV videos background tune. Are you planning on doing more UVM videos?
Yes I'm doing it. It's just taking time to prepare the materials