SystemVerilog Tutorial in 5 Minutes 19 - Compiler Directives

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  • Опубліковано 22 гру 2024

КОМЕНТАРІ • 17

  • @buiw138
    @buiw138 2 місяці тому

    Very helpful, now I have only one video remaining. I am going to watch it tomorrow, once again thanks for your series.

    • @openlogic925
      @openlogic925  2 місяці тому

      Thanks. Glad it has been helpful🙂

  • @johnaaronalmarez1267
    @johnaaronalmarez1267 Рік тому

    Thank you so much for all the videos. Its very helpful to me. Looking forward for more SV tutorials and more UVM tutorials as well!

  • @malikshanaah9804
    @malikshanaah9804 Рік тому +2

    Can't imagine that you can put an extensive-detailed Book Chapter (40 pages) in ONLY 5 mins!
    A bunch of thx, Sir!
    Good bless you!

    • @openlogic925
      @openlogic925  Рік тому +1

      Thanks! I'm sure the book covers more. But I do try to summarize the fundamental and the commonly used feature 😊

    • @malikshanaah9804
      @malikshanaah9804 Рік тому

      @@openlogic925
      Yup! Sure! But the Book is usually hard to follow and put all things together

  • @Jun-um4rl
    @Jun-um4rl Рік тому

    Thank you so much for all the videos, you are a great explainer and I hope you keep making systemverilog and uvm tutorials!

    • @openlogic925
      @openlogic925  Рік тому

      Thanks for the kind comment. I'll do my best 🙂

  • @Zanzara0403
    @Zanzara0403 Рік тому

    Wow, this section is very useful. Could you please share the document you referred to?

    • @Zanzara0403
      @Zanzara0403 Рік тому

      Is this supported only by SystemVerilog, or does it also work in Verilog?

    • @openlogic925
      @openlogic925  Рік тому +1

      For the first question, I re-watched the video. I didn't mention any document. So I'm not sure which document you're talking about. For the second question, it's been a long time since I last used Verilog, so I'm not sure if compiler directives are supported there.

  • @bhagyashreeaher8905
    @bhagyashreeaher8905 Рік тому

    Sir thank you for all system verilog videos
    Please make more system verilog videos for beginners in-depth video with UVM

  • @timothydahlin5321
    @timothydahlin5321 Рік тому

    What you mention at 1:29 is called an "include guard".

    • @openlogic925
      @openlogic925  Рік тому

      Thanks. I never realize there's a term for it.

    • @timothydahlin5321
      @timothydahlin5321 Рік тому

      @@openlogic925 Good concise SV & DIMM background videos. Not a fan of the SV videos background tune. Are you planning on doing more UVM videos?

    • @openlogic925
      @openlogic925  Рік тому

      Yes I'm doing it. It's just taking time to prepare the materials